18 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Aadi Desai	5c8daf3ea0	Add fixes and documentation	2022-12-16 22:16:17 +00:00
Alden0012	8ae5a07fca	add updated vga files	2022-12-16 22:11:31 +00:00
Alden0012	3c60629d48	Add scripts/rtl for formal verification	2022-12-16 20:19:07 +00:00
Aadi Desai	827ed444fa	Fixes and adding missing setup.do script for vsim	2022-12-12 16:49:07 +00:00
Alden0012	5c4334ab76	Merge branch 'main' of github.com:supleed2/hsvcw into main	2022-12-12 16:16:23 +00:00
Alden0012	aabd220e6a	Increase covergroups and test inputs for VGA, Integrate gpio checker in tb	2022-12-12 16:16:17 +00:00
Aadi Desai	9c9536016b	Format top tb and add vga image buffer reset task	2022-12-12 16:05:01 +00:00
Alden0012	f586cd95d9	Add VGA and GPIO checker	2022-12-05 16:55:23 +00:00
Aadi Desai	f9bd753cde	Add coursework requirements document	2022-12-02 14:01:20 +00:00
Alden0012	128a2a9eaa	Fix GPIO assertions and test-bench coverage and constraints	2022-11-14 15:28:45 +00:00
Alden0012	f2b3a72a54	Add initial GPIO test-bench	2022-11-14 10:24:11 +00:00
Alden0012	f50d0c5c2e	Add redundant VGA and comparator module	2022-11-08 17:49:23 +00:00
Alden0012	4edfce0e03	Add initial assume to AHBGPIO.sv	2022-11-08 17:27:39 +00:00
Alden0012	0f8578e1b8	Add assertions to AHBGPIO.sv	2022-11-08 17:04:59 +00:00
Aadi Desai	0d4099ce15	Update AHBVGASYS.sv to SystemVerilog and style	2022-11-07 13:57:19 +00:00
Aadi Desai	018013d3c8	Add parity generation and checking to AHBGPIO.sv	2022-11-07 13:36:56 +00:00
Aadi Desai	c83b8a73f1	Switch all Verilog files to SystemVerilog file endings	2022-11-07 12:58:43 +00:00
Aadi Desai	dcdda4d9e1	Initial Commit	2022-11-07 12:41:05 +00:00