supleed2/ELEC70056-HSV-CW2
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About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements
4 commits 1 branch 0 tags 3.8 MiB
SystemVerilog 96.4%
Assembly 3.2%
Tcl 0.2%
Makefile 0.2%
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Aadi Desai 0d4099ce15 Update AHBVGASYS.sv to SystemVerilog and style
2022-11-07 13:57:19 +00:00
docs Initial Commit 2022-11-07 12:41:05 +00:00
rtl Update AHBVGASYS.sv to SystemVerilog and style 2022-11-07 13:57:19 +00:00
src Initial Commit 2022-11-07 12:41:05 +00:00
tbench Switch all Verilog files to SystemVerilog file endings 2022-11-07 12:58:43 +00:00
ahblite_sys.vc Initial Commit 2022-11-07 12:41:05 +00:00
readme.txt Initial Commit 2022-11-07 12:41:05 +00:00

readme.txt 

For simulation purposes, place the code.hex file in the same root directory where you launch the Questasim simulation