Switch all Verilog files to SystemVerilog file endings

2024-09-19 20:56:18 +00:00 · 2022-11-07 12:58:43 +00:00 · 2022-11-07 12:58:43 +00:00 · c83b8a73f1
parent dcdda4d9e1
commit c83b8a73f1
13 changed files with 0 additions and 0 deletions
--- a/rtl/AHBLITE_SYS.sv
+++ b/rtl/AHBLITE_SYS.sv
--- a/rtl/AHB_BRAM/AHB2BRAM.sv
+++ b/rtl/AHB_BRAM/AHB2BRAM.sv
--- a/rtl/AHB_BUS/AHBDCD.sv
+++ b/rtl/AHB_BUS/AHBDCD.sv
--- a/rtl/AHB_BUS/AHBMUX.sv
+++ b/rtl/AHB_BUS/AHBMUX.sv
--- a/rtl/AHB_GPIO/AHBGPIO.sv
+++ b/rtl/AHB_GPIO/AHBGPIO.sv
--- a/rtl/AHB_VGA/AHBVGASYS.sv
+++ b/rtl/AHB_VGA/AHBVGASYS.sv
--- a/rtl/AHB_VGA/counter.sv
+++ b/rtl/AHB_VGA/counter.sv
--- a/rtl/AHB_VGA/dual_port_ram_sync.sv
+++ b/rtl/AHB_VGA/dual_port_ram_sync.sv
--- a/rtl/AHB_VGA/font_rom.sv
+++ b/rtl/AHB_VGA/font_rom.sv
--- a/rtl/AHB_VGA/vga_console.sv
+++ b/rtl/AHB_VGA/vga_console.sv
--- a/rtl/AHB_VGA/vga_image.sv
+++ b/rtl/AHB_VGA/vga_image.sv
--- a/rtl/AHB_VGA/vga_sync.sv
+++ b/rtl/AHB_VGA/vga_sync.sv
--- a/tbench/ahblite_sys_tb.sv
+++ b/tbench/ahblite_sys_tb.sv