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Increase covergroups and test inputs for VGA, Integrate gpio checker in tb

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This commit is contained in:
Alden0012 2022-12-12 16:16:17 +00:00
parent f586cd95d9
commit aabd220e6a
7 changed files with 230 additions and 167 deletions
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17
Makefile Normal file
View file

@ -0,0 +1,17 @@
gpio:
vlog -work work +acc=blnr +cover -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
vopt -work work ahb_gpio_tb -o work_opt
vsim -coverage work_opt -do setup.do -l sim.log
vga:
vlog -work work +acc=blnr +cover -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
vopt -work work ahb_vga_tb -o work_opt
vsim -coverage work_opt -do setup.do -l sim.log
sys:
vlog -work work +acc=blnr -noincr -timescale 1ns/1ps rtl/**/*.sv tbench/*.sv
vopt -work work ahblite_sys_tb -o work_opt
vsim work_opt -do setup.do -l sim.log
# jg:
# jg rtl/AHB_GPIO/AHBGPIO.tcl

76
rtl/AHB_GPIO/AHBGPIO.sv
View file

@ -114,46 +114,46 @@ module AHBGPIO
//check behaviour
assert_parity: assert property
( @(posedge HCLK) disable iff (!HRESETn)
!PARITYERR
);
// assert_parity: assert property
// ( @(posedge HCLK) disable iff (!HRESETn)
// !PARITYERR
// );
assert_gpio_write: assert property
( @(posedge HCLK) disable iff (!HRESETn)
((HADDR[7:0] == gpio_data_addr)
&& HSEL
&& HWRITE
&& HTRANS[1]
&& HREADY) |-> ##1
(gpio_dir == 16'h0001) |-> ##1
(GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
);
assert_gpio_read: assert property
( @(posedge HCLK) disable iff (!HRESETn)
((gpio_dir == 16'h0000)
&& (HADDR[7:0] == gpio_data_addr)
// && HSEL // HSEL not used in Read always_ff
&& !HWRITE
&& HTRANS[1]
&& HREADY) |-> ##1
((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
);
// assert_gpio_write: assert property
// ( @(posedge HCLK) disable iff (!HRESETn)
// ((HADDR[7:0] == gpio_data_addr)
// && HSEL
// && HWRITE
// && HTRANS[1]
// && HREADY) |-> ##1
// (gpio_dir == 16'h0001) |-> ##1
// (GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
// );
// assert_gpio_read: assert property
// ( @(posedge HCLK) disable iff (!HRESETn)
// ((gpio_dir == 16'h0000)
// && (HADDR[7:0] == gpio_data_addr)
// // && HSEL // HSEL not used in Read always_ff
// && !HWRITE
// && HTRANS[1]
// && HREADY) |-> ##1
// ((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
// );
assert_gpio_dir: assert property
( @(posedge HCLK) disable iff (!HRESETn)
((HADDR[7:0] == gpio_dir_addr)
&& HSEL
&& HWRITE
&& HTRANS[1]
&& HREADY) |-> ##1
((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
);
// assert_gpio_dir: assert property
// ( @(posedge HCLK) disable iff (!HRESETn)
// ((HADDR[7:0] == gpio_dir_addr)
// && HSEL
// && HWRITE
// && HTRANS[1]
// && HREADY) |-> ##1
// ((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
// );
assume_initial_valid: assume property
( @(posedge HCLK)
gpio_dir == 16'h0000
|| gpio_dir == 16'h0001
);
// assume_initial_valid: assume property
// ( @(posedge HCLK)
// gpio_dir == 16'h0000
// || gpio_dir == 16'h0001
// );
endmodule

26
rtl/AHB_GPIO/ahb_gpio_checker.sv
View file

@ -1,15 +1,13 @@
module ahb_gpio_checker
( input wire HCLK
, input wire HRESETn
, input wire [31:0] HADDR
, input wire [ 1:0] HTRANS
, input wire [31:0] HWDATA
, input wire HWRITE
, input wire HSEL
, input wire HREADY
, input wire [16:0] GPIOIN
, input wire PARITYSEL
, input wire INJECT_FAULT
( input wire HCLK
, input wire HRESETn
, input wire [31:0] HADDR
, input wire [ 1:0] HTRANS
, input wire [31:0] HWDATA
, input wire HWRITE
, input wire HSEL
, input wire HREADY
, input wire [16:0] GPIOIN
, input wire HREADYOUT
, input wire [31:0] HRDATA
, input wire [16:0] GPIOOUT
@ -27,15 +25,15 @@ module ahb_gpio_checker
@(posedge HCLK) disable iff (!HRESETn)
(HADDR[7:0] == gpio_data_addr) && gpio_cmd
##1
(gpio_dir=='1)
(gpio_dir=='1) |->
##1
(GPIOOUT[15:0] == $past(HWDATA,1));
(GPIOOUT[15:0] == $past(HWDATA[15:0],1));
endproperty
property gpio_read;
@(posedge HCLK) disable iff (!HRESETn)
(HADDR[7:0] == gpio_data_addr) && gpio_cmd
&& (gpio_dir=='0)
&& (gpio_dir=='0) |->
##1
((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT);
endproperty

168
rtl/AHB_VGA/AHBVGASYS.sv
View file

@ -3,7 +3,7 @@
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (<EFBFBD>LICENCE<EFBFBD>) IS A LEGAL AGREEMENT BETWEEN //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
@ -34,20 +34,23 @@
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBVGA
( input wire HCLK
, input wire HRESETn
, input wire [31:0] HADDR
, input wire [31:0] HWDATA
, input wire HREADY
, input wire HWRITE
, input wire [1:0] HTRANS
, input wire HSEL
, output wire [31:0] HRDATA
, output wire HREADYOUT
, output wire HSYNC
, output wire VSYNC
, output wire [7:0] RGB
module AHBVGA(
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HREADY,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HSEL,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire HSYNC,
output wire VSYNC,
output wire [7:0] RGB
);
//Register locations
localparam IMAGEADDR = 4'hA;
@ -76,11 +79,13 @@ module AHBVGA
wire sel_image;
reg [7:0] cin;
always_ff @(posedge HCLK)
if(HREADY) begin
last_HADDR <= HADDR;
always @(posedge HCLK)
if(HREADY)
begin
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
last_HSEL <= HSEL;
last_HTRANS <= HTRANS;
end
@ -88,71 +93,87 @@ module AHBVGA
assign HREADYOUT = ~scroll;
//VGA interface: control the synchronization and color signals for a particular resolution
VGAInterface uVGAInterface
( .CLK (HCLK)
, .COLOUR_IN (cin)
, .cout (RGB)
, .hs (HSYNC)
, .vs (VSYNC)
, .addrh (pixel_x)
, .addrv (pixel_y)
);
VGAInterface uVGAInterface (
.CLK(HCLK),
.resetn(HRESETn),
.COLOUR_IN(cin),
.cout(RGB),
.hs(HSYNC),
.vs(VSYNC),
.addrh(pixel_x),
.addrv(pixel_y)
);
//VGA console module: output the pixels in the text region
vga_console uvga_console
( .clk (HCLK)
, .resetn (HRESETn)
, .pixel_x (pixel_x)
, .pixel_y (pixel_y)
, .text_rgb (console_rgb)
, .font_we (console_write)
, .font_data (console_wdata)
, .scroll (scroll)
);
vga_console uvga_console(
.clk(HCLK),
.resetn(HRESETn),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.text_rgb(console_rgb),
.font_we(console_write),
.font_data(console_wdata),
.scroll(scroll)
);
//VGA image buffer: output the pixels in the image region
vga_image uvga_image
( .clk (HCLK)
, .resetn (HRESETn)
, .address (last_HADDR[15:2])
, .pixel_x (pixel_x)
, .pixel_y (pixel_y)
, .image_we (image_write)
, .image_data (image_wdata)
, .image_rgb (image_rgb)
);
vga_image uvga_image(
.clk(HCLK),
.resetn(HRESETn),
.address(last_HADDR[15:2]),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.image_we(image_write),
.image_data(image_wdata),
.image_rgb(image_rgb)
);
assign sel_console = (last_HADDR[23:0] == 12'h000000000000);
assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
assign sel_console = (last_HADDR[23:0]== 12'h000000000000);
assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
//Set console write and write data
always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) begin
console_write <= 0;
console_wdata <= 0;
end else if (last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console) begin
console_write <= 1'b1;
console_wdata <= HWDATA[7:0];
end else begin
console_write <= 1'b0;
console_wdata <= 0;
end
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
console_write <= 0;
console_wdata <= 0;
end
else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console)
begin
console_write <= 1'b1;
console_wdata <= HWDATA[7:0];
end
else
begin
console_write <= 1'b0;
console_wdata <= 0;
end
end
//Set image write and image write data
always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) begin
image_write <= 0;
image_wdata <= 0;
end else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image) begin
image_write <= 1'b1;
image_wdata <= HWDATA[7:0];
end else begin
image_write <= 1'b0;
image_wdata <= 0;
end
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
image_write <= 0;
image_wdata <= 0;
end
else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image)
begin
image_write <= 1'b1;
image_wdata <= HWDATA[7:0];
end
else
begin
image_write <= 1'b0;
image_wdata <= 0;
end
end
//Select the rgb color for a particular region
always_comb
always @*
begin
if(!HRESETn)
cin <= 8'h00;
else
@ -160,6 +181,7 @@ module AHBVGA
cin <= console_rgb ;
else
cin <= image_rgb;
end
endmodule

43
rtl/AHB_VGA/ahb_vgasys_checker.sv
View file

@ -62,32 +62,33 @@ module ahb_vgasys_checker(
begin
pixel_x <= 0;
pixel_y <= 0;
console_text_reg <= "";
counter <= 0;
if(!HRESETn)
console_text_reg <= "";
counter <= 0;
countup <= 0;
end
else
begin
countup <= countup + 1;
if($past(HSEL && HREADY && HWRITE && (HADDR[23:0]== 12'h000000000000),1) && HREADYOUT)
begin
console_text_reg <= {console_text_reg,font_map[HWDATA]};
character_buffer[counter] <= HWDATA[7:0];
counter <= counter+1;
end
if($fell(vgaif.HSYNC))
begin
pixel_x <= 0;
pixel_y <= pixel_y + 1;
end
else
begin
if(vgaif.HSYNC)
if(countup)
begin
pixel_x <= pixel_x + 1;
end
end
if($past(HSEL && HREADY && HWRITE && (HADDR[23:0]== 12'h000000000000),1) && HREADYOUT)
begin
console_text_reg <= {console_text_reg,font_map[HWDATA]};
character_buffer[counter] <= HWDATA[7:0];
counter <= counter+1;
end
if($fell(vgaif.HSYNC))
begin
pixel_x <= 0;
pixel_y <= pixel_y + 1;
end
else
begin
if(vgaif.HSYNC)
if(countup)
begin
pixel_x <= pixel_x + 1;
end
end
end
end

43
tbench/ahb_gpio_tb.sv
View file

@ -39,6 +39,7 @@ module ahb_gpio_tb;
localparam max_test_count = 1000;
logic parity_sel = '0;
logic parity_err;
integer test_count;
ahb_gpio_if gpioif();
@ -54,10 +55,26 @@ module ahb_gpio_tb;
.GPIOIN (gpioif.GPIOIN),
.PARITYSEL (parity_sel),
.INJECT_FAULT ('0),
.HREADYOUT (gpioif.HREADYOUT),
.HREADYOUT (gpioif.HREADYOUT),
.HRDATA (gpioif.HRDATA),
.GPIOOUT (gpioif.GPIOOUT),
.PARITYERR ()
.PARITYERR (parity_err)
);
ahb_gpio_checker gpio_checker(
.HCLK (gpioif.HCLK),
.HRESETn (gpioif.HRESETn),
.HADDR (gpioif.HADDR),
.HTRANS (gpioif.HTRANS),
.HWDATA (gpioif.HWDATA),
.HWRITE (gpioif.HWRITE),
.HSEL (gpioif.HSEL),
.HREADY (gpioif.HREADY),
.GPIOIN (gpioif.GPIOIN),
.HREADYOUT (gpioif.HREADYOUT),
.HRDATA (gpioif.HRDATA),
.GPIOOUT (gpioif.GPIOOUT),
.PARITYERR (parity_err)
);
class gpio_stimulus;
@ -121,20 +138,20 @@ module ahb_gpio_tb;
endgroup
covergroup cover_ahb_write_values;
covergroup cover_hwdata_values;
coverpoint gpioif.HWDATA;
endgroup
covergroup cover_ahb_read_values;
coverpoint gpioif.HRDATA;
covergroup cover_hrdata_values;
coverpoint gpioif.HRDATA[15:0];
endgroup
covergroup cover_gpio_in_values;
coverpoint gpioif.GPIOIN;
coverpoint gpioif.GPIOIN[15:0];
endgroup
covergroup cover_gpio_out_values;
coverpoint gpioif.GPIOOUT;
coverpoint gpioif.GPIOOUT[15:0];
endgroup
task deassert_reset();
@ -147,13 +164,13 @@ module ahb_gpio_tb;
endtask
initial begin
cover_ahb_write_values covahbwrite;
cover_ahb_read_values covahbread;
cover_hwdata_values covhwdata;
cover_hrdata_values covhrdata;
cover_gpio_in_values covgpioin;
cover_gpio_out_values covgpioout;
cover_ahb_transaction_vals covahbtransactionvals;
covahbwrite = new();
covahbread = new();
covhwdata = new();
covhrdata = new();
covgpioin = new();
covgpioout = new();
covahbtransactionvals = new();
@ -171,9 +188,9 @@ module ahb_gpio_tb;
gpioif.HADDR = stimulus_vals.HADDR;
gpioif.GPIOIN = stimulus_vals.GPIOIN;
covahbwrite.sample();
covhwdata.sample();
covgpioin.sample();
covahbread.sample();
covhrdata.sample();
covgpioout.sample();
covahbtransactionvals.sample();

24
tbench/ahb_vga_tb.sv
View file

@ -76,7 +76,7 @@ module ahb_vga_tb;
);
logic display_enable;
integer reset_time;
task deassert_reset();
begin
vgaif.HRESETn = 0;
@ -118,7 +118,7 @@ module ahb_vga_tb;
endtask
class vga_stimulus;
rand logic [31:0] HWDATA;
randc logic [31:0] HWDATA;
constraint c_hwdata
{0 <= HWDATA; HWDATA <= 8'h7f;}
@ -128,32 +128,40 @@ module ahb_vga_tb;
covergroup cover_vga_chars;
cp_hwdata: coverpoint vgaif.HWDATA{
bins invalid = {[128:255]};
option.auto_bin_max = 128;
bins lo_1 = {[0:15]};
bins lo_2 = {[16:31]};
bins mid_1 = {[32:47]};
bins mid_2 = {[48:63]};
bins mid_3 = {[64:79]};
bins mid_4 = {[80:95]};
bins hi_1 = {[96:111]};
bins hi_2 = {[112:127]};
}
endgroup
integer char_index;
string test_value = "";
initial begin
cover_vga_chars covvgachars;
covvgachars = new();
stimulus_vals = new();
deassert_reset();
display_enable = 0;
deassert_reset();
display_enable = 1;
test_value = "";
@(posedge vgaif.VSYNC);
display_enable = 1;
$display(test_value);
for(char_index = 0; char_index < 16; char_index++)
for(char_index = 0; char_index < 30; char_index++)
begin
assert (stimulus_vals.randomize) else $fatal;
setChar(stimulus_vals.HWDATA);
covvgachars.sample();
test_value = {test_value, font_map[stimulus_vals.HWDATA]};
end
setChar(8'h08);
// setChar(8'h08);
// setChar(8'h54);
// setChar(8'h45);
// setChar(8'h53);