mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-11-10 02:15:47 +00:00
187 lines
4 KiB
Systemverilog
187 lines
4 KiB
Systemverilog
// stub
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interface ahb_vga_if;
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typedef enum bit[1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQUENTIAL = 2'b10,
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SEQUENTIAL = 2'b11
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} htrans_types;
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logic HCLK;
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logic HRESETn;
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logic [31:0] HADDR;
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logic [ 1:0] HTRANS;
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logic [31:0] HWDATA;
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logic HWRITE;
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logic HSEL;
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logic HREADY;
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logic HREADYOUT;
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logic [31:0] HRDATA;
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logic [7:0] RGB;
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logic HSYNC;
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logic VSYNC;
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modport DUT
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( input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY,
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output HREADYOUT, HRDATA, RGB, HSYNC, VSYNC
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);
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modport TB
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( input HCLK, HREADYOUT, HRDATA, RGB, HSYNC, VSYNC,
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output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL
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);
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endinterface
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module ahb_vga_tb;
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import ahb_vga_font_map::*;
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localparam IMAGEADDR = 4'hA;
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localparam CONSOLEADDR = 4'h0;
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ahb_vga_if vgaif();
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AHBVGA vga(
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.HCLK(vgaif.HCLK),
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.HRESETn(vgaif.HRESETn),
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.HADDR(vgaif.HADDR),
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.HWDATA(vgaif.HWDATA),
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.HREADY(vgaif.HREADY),
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.HWRITE(vgaif.HWRITE),
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.HTRANS(vgaif.HTRANS),
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.HSEL(vgaif.HSEL),
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.HRDATA(vgaif.HRDATA),
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.HREADYOUT(vgaif.HREADYOUT),
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.HSYNC(vgaif.HSYNC),
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.VSYNC(vgaif.VSYNC),
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.RGB(vgaif.RGB)
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);
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logic [7:0] checker_rgb;
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ahb_vgasys_checker vga_checker(
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.HCLK(vgaif.HCLK),
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.HRESETn(vgaif.HRESETn),
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.HADDR(vgaif.HADDR),
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.HWDATA(vgaif.HWDATA),
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.HREADY(vgaif.HREADY),
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.HWRITE(vgaif.HWRITE),
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.HTRANS(vgaif.HTRANS),
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.HSEL(vgaif.HSEL),
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.HRDATA(vgaif.HRDATA),
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.HREADYOUT(vgaif.HREADYOUT),
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.HSYNC(vgaif.HSYNC),
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.VSYNC(vgaif.VSYNC),
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.RGB(vgaif.RGB),
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.checker_rgb_out(checker_rgb)
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);
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logic display_enable;
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integer reset_time;
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task deassert_reset();
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begin
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vgaif.HRESETn = 0;
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@(posedge vgaif.HCLK);
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@(posedge vgaif.HCLK);
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vgaif.HRESETn = 1;
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end
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endtask
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initial begin
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vgaif.HCLK = 0;
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forever #20 vgaif.HCLK = ! vgaif.HCLK;
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end
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string line;
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always @(posedge vgaif.HCLK) begin
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if(display_enable)
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if ($fell(vgaif.HSYNC)) begin
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$display(line);
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line = "";
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end else if (vgaif.HSYNC)
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if (checker_rgb == 8'd28)
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line = {line, "#"};
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else
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line = {line, "."};
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end
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task setChar(input bit [7:0] c);
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@(posedge vgaif.HCLK);
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vgaif.HREADY = 1;
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vgaif.HWRITE = 1;
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vgaif.HTRANS = 2'b10;
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vgaif.HSEL = 1;
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vgaif.HADDR = 32'h50000000;
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@(posedge(vgaif.HCLK));
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vgaif.HWDATA = c;
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vgaif.HWRITE = 0;
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@(posedge (vgaif.HCLK && vgaif.HREADYOUT));
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endtask
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class vga_stimulus;
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randc logic [31:0] HWDATA;
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constraint c_hwdata
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{0 <= HWDATA; HWDATA <= 8'h7f;}
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endclass
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vga_stimulus stimulus_vals;
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covergroup cover_vga_chars;
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cp_hwdata: coverpoint vgaif.HWDATA{
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bins lo_1 = {[0:15]};
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bins lo_2 = {[16:31]};
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bins mid_1 = {[32:47]};
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bins mid_2 = {[48:63]};
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bins mid_3 = {[64:79]};
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bins mid_4 = {[80:95]};
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bins hi_1 = {[96:111]};
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bins hi_2 = {[112:127]};
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}
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endgroup
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integer char_index;
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string test_value = "";
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initial begin
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cover_vga_chars covvgachars;
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covvgachars = new();
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stimulus_vals = new();
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display_enable = 0;
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deassert_reset();
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display_enable = 1;
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test_value = "";
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@(posedge vgaif.VSYNC);
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display_enable = 1;
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$display(test_value);
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for(char_index = 0; char_index < 30; char_index++)
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begin
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assert (stimulus_vals.randomize) else $fatal;
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setChar(stimulus_vals.HWDATA);
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covvgachars.sample();
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test_value = {test_value, font_map[stimulus_vals.HWDATA]};
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end
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// setChar(8'h08);
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// setChar(8'h54);
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// setChar(8'h45);
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// setChar(8'h53);
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// setChar(8'h54);
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// setChar(8'h21);
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// setChar(8'h00);
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vgaif.HREADY = '0;
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vgaif.HWRITE = '0;
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vgaif.HTRANS = '0;
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vgaif.HSEL = '0;
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vgaif.HADDR = '0;
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vgaif.HWDATA = '0;
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@(posedge vgaif.VSYNC);
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$display(test_value);
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$stop;
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end
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logic rgb_active;
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assign rgb_active = (vgaif.RGB==8'h1c);
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logic checker_rgb_active;
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assign checker_rgb_active = (checker_rgb==8'h1c);
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endmodule |