mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-09-19 20:56:18 +00:00
Add VGA and GPIO checker
This commit is contained in:
Alden0012
parent
f9bd753cde
commit
f586cd95d9
67
rtl/AHB_GPIO/ahb_gpio_checker.sv
Normal file
67
rtl/AHB_GPIO/ahb_gpio_checker.sv
Normal file
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@ -0,0 +1,67 @@
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module ahb_gpio_checker
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( input wire HCLK
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, input wire HRESETn
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, input wire [31:0] HADDR
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, input wire [ 1:0] HTRANS
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, input wire [31:0] HWDATA
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, input wire HWRITE
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, input wire HSEL
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, input wire HREADY
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, input wire [16:0] GPIOIN
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, input wire PARITYSEL
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, input wire INJECT_FAULT
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, input wire HREADYOUT
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, input wire [31:0] HRDATA
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, input wire [16:0] GPIOOUT
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, input wire PARITYERR
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);
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logic gpio_cmd = HSEL && HREADY && HTRANS[1];
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logic gpio_dir;
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localparam [7:0] gpio_data_addr = 8'h00;
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localparam [7:0] gpio_dir_addr = 8'h04;
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// defined properties
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property gpio_write;
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@(posedge HCLK) disable iff (!HRESETn)
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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##1
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(gpio_dir=='1)
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##1
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(GPIOOUT[15:0] == $past(HWDATA,1));
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endproperty
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property gpio_read;
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@(posedge HCLK) disable iff (!HRESETn)
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(HADDR[7:0] == gpio_data_addr) && gpio_cmd
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&& (gpio_dir=='0)
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##1
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((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT);
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endproperty
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always_ff @(posedge HCLK)
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begin
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if(!HRESETn)
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begin
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gpio_dir <= '0;
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end
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else
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begin
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if($past((gpio_cmd && (HADDR == gpio_dir_addr)),1))
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begin
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gpio_dir <= HWDATA;
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end
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end
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end
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// check behaviour
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assert_parity: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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!PARITYERR
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);
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assert_gpio_write: assert property (gpio_write);
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assert_gpio_read: assert property (gpio_read);
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endmodule
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@ -18,6 +18,6 @@ module VGACOMPARATOR
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&& HSYNC1 == HSYNC2
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&& VSYNC1 == VSYNC2
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&& RGB1 == RGB2
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)
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);
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endmodule
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165
rtl/AHB_VGA/ahb_vgasys_checker.sv
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165
rtl/AHB_VGA/ahb_vgasys_checker.sv
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@ -0,0 +1,165 @@
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module ahb_vgasys_checker(
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input wire HCLK,
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input wire HRESETn,
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input wire [31:0] HADDR,
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input wire [31:0] HWDATA,
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input wire HREADY,
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input wire HWRITE,
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input wire [1:0] HTRANS,
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input wire HSEL,
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input wire [31:0] HRDATA,
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input wire HREADYOUT,
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input wire HSYNC,
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input wire VSYNC,
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input wire [7:0] RGB,
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output wire [7:0] checker_rgb_out
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);
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import ahb_vga_font_map::*;
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// NOTE: Due to a BUG in the VGA module, the first 2 pixels for each row in the visible region is invalid, the actual image starts 2 cycles later
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localparam text_region_x_min = 48 + 2;
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localparam text_region_x_max = text_region_x_min + 240 - 2;
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localparam text_region_y_min = 29;
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localparam text_region_y_max = text_region_y_min + 480;
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localparam character_width = 8;
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localparam character_height = 16;
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localparam characters_per_row = 240/character_width;
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localparam characters_per_col = 480/character_height;
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logic [31:0] counter;
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logic countup;
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int pixel_x;
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int pixel_y;
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//local coords within the visible text region
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int frame_x;
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int frame_y;
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//local coords within the tile
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logic [2:0] character_x;
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logic [3:0] character_y;
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logic [7:0] checker_rgb;
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logic [7:0] character_buffer[characters_per_row*characters_per_col];
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string console_text_reg;
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int hcounter;
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int vcounter;
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function logic inTextRegion(int x, int y);
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return (x >= text_region_x_min && x <= text_region_x_max) && (y >= text_region_y_min && y <= text_region_y_max);
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endfunction
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function int getStringIndex(int x, int y);
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return (((y/character_height)*characters_per_row)+ (x/character_width));
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endfunction
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function logic[7:0] getRGBvalue(logic[2:0] x, logic[3:0] y, int char_index);
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return font_lookup({char_index, y})[7-x] ? 8'h1c : 8'h00;
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endfunction
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always_ff @(posedge HCLK)
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begin
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if(!HRESETn || !VSYNC)
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begin
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pixel_x <= 0;
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pixel_y <= 0;
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console_text_reg <= "";
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counter <= 0;
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countup <= 0;
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end
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else
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begin
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countup <= countup + 1;
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if($past(HSEL && HREADY && HWRITE && (HADDR[23:0]== 12'h000000000000),1) && HREADYOUT)
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begin
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console_text_reg <= {console_text_reg,font_map[HWDATA]};
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character_buffer[counter] <= HWDATA[7:0];
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counter <= counter+1;
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end
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if($fell(vgaif.HSYNC))
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begin
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pixel_x <= 0;
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pixel_y <= pixel_y + 1;
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end
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else
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begin
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if(vgaif.HSYNC)
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if(countup)
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begin
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pixel_x <= pixel_x + 1;
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end
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end
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end
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end
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always_ff @(posedge HCLK)
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begin
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if(!HRESETn)
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begin
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hcounter <= 0;
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vcounter <= 0;
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end
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else
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begin
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if($fell(VSYNC))
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vcounter <= 0;
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else
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if($fell(HSYNC))
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vcounter <= vcounter + 1;
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if($fell(HSYNC))
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hcounter <= 0;
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else
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hcounter <= hcounter + 1;
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end
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end
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always_comb
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begin
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checker_rgb = 0;
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frame_x = pixel_x - text_region_x_min;
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frame_y = pixel_y - text_region_y_min;
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character_x = frame_x % character_width;
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character_y = frame_y % character_height;
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if(inTextRegion(pixel_x,pixel_y))
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begin
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if(getStringIndex(frame_x,frame_y) < console_text_reg.len())
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begin
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checker_rgb = getRGBvalue(character_x,character_y,character_buffer[getStringIndex(frame_x,frame_y)]);
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//$display("char: %s, x: 0x%0h, y: 0x%0h",console_text_reg.substr(getStringIndex(frame_x,frame_y),getStringIndex(frame_x,frame_y)), frame_x, frame_y);
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end
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end
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end
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assign checker_rgb_out = checker_rgb;
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//assertions
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assert_text_region: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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(inTextRegion(pixel_x,pixel_y) && (frame_x > 1)) -> (checker_rgb == RGB)
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);
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assert_vsync_pulse_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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$rose(VSYNC) -> (($past(vcounter,1) == 8'h1) || (vcounter == '0))
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);
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assert_hsync_pulse_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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($rose(HSYNC) && !$rose(VSYNC) && VSYNC) -> ($past(hcounter,1)/2 == 8'd95)
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);
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assert_line_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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($fell(HSYNC) && !$rose(VSYNC) && VSYNC) -> ($past(hcounter,1)/2 == 800)
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);
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assert_frame_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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$fell(VSYNC) -> (($past(vcounter,1) == (32'd480 + 32'd10 + 32'd2 + 32'd29)) || (vcounter == '0))
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);
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endmodule
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2316
tbench/ahb_vga_font_map.sv
Normal file
2316
tbench/ahb_vga_font_map.sv
Normal file
File diff suppressed because it is too large
Load diff
179
tbench/ahb_vga_tb.sv
Normal file
179
tbench/ahb_vga_tb.sv
Normal file
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@ -0,0 +1,179 @@
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// stub
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interface ahb_vga_if;
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typedef enum bit[1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQUENTIAL = 2'b10,
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SEQUENTIAL = 2'b11
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} htrans_types;
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logic HCLK;
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logic HRESETn;
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logic [31:0] HADDR;
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logic [ 1:0] HTRANS;
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logic [31:0] HWDATA;
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logic HWRITE;
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logic HSEL;
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logic HREADY;
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logic HREADYOUT;
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logic [31:0] HRDATA;
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logic [7:0] RGB;
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logic HSYNC;
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logic VSYNC;
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modport DUT
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( input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY,
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output HREADYOUT, HRDATA, RGB, HSYNC, VSYNC
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);
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modport TB
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( input HCLK, HREADYOUT, HRDATA, RGB, HSYNC, VSYNC,
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output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL
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);
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endinterface
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module ahb_vga_tb;
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import ahb_vga_font_map::*;
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localparam IMAGEADDR = 4'hA;
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localparam CONSOLEADDR = 4'h0;
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ahb_vga_if vgaif();
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AHBVGA vga(
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.HCLK(vgaif.HCLK),
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.HRESETn(vgaif.HRESETn),
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.HADDR(vgaif.HADDR),
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.HWDATA(vgaif.HWDATA),
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.HREADY(vgaif.HREADY),
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.HWRITE(vgaif.HWRITE),
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.HTRANS(vgaif.HTRANS),
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.HSEL(vgaif.HSEL),
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.HRDATA(vgaif.HRDATA),
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.HREADYOUT(vgaif.HREADYOUT),
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.HSYNC(vgaif.HSYNC),
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.VSYNC(vgaif.VSYNC),
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.RGB(vgaif.RGB)
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);
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logic [7:0] checker_rgb;
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ahb_vgasys_checker vga_checker(
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.HCLK(vgaif.HCLK),
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.HRESETn(vgaif.HRESETn),
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.HADDR(vgaif.HADDR),
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.HWDATA(vgaif.HWDATA),
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.HREADY(vgaif.HREADY),
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.HWRITE(vgaif.HWRITE),
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.HTRANS(vgaif.HTRANS),
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.HSEL(vgaif.HSEL),
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.HRDATA(vgaif.HRDATA),
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.HREADYOUT(vgaif.HREADYOUT),
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.HSYNC(vgaif.HSYNC),
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.VSYNC(vgaif.VSYNC),
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.RGB(vgaif.RGB),
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.checker_rgb_out(checker_rgb)
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);
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logic display_enable;
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task deassert_reset();
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begin
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vgaif.HRESETn = 0;
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@(posedge vgaif.HCLK);
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@(posedge vgaif.HCLK);
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vgaif.HRESETn = 1;
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end
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endtask
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initial begin
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vgaif.HCLK = 0;
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forever #20 vgaif.HCLK = ! vgaif.HCLK;
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end
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string line;
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always @(posedge vgaif.HCLK) begin
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if(display_enable)
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if ($fell(vgaif.HSYNC)) begin
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$display(line);
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line = "";
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end else if (vgaif.HSYNC)
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if (checker_rgb == 8'd28)
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line = {line, "#"};
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else
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line = {line, "."};
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end
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task setChar(input bit [7:0] c);
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@(posedge vgaif.HCLK);
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vgaif.HREADY = 1;
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vgaif.HWRITE = 1;
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vgaif.HTRANS = 2'b10;
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vgaif.HSEL = 1;
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vgaif.HADDR = 32'h50000000;
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@(posedge(vgaif.HCLK));
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vgaif.HWDATA = c;
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vgaif.HWRITE = 0;
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@(posedge (vgaif.HCLK && vgaif.HREADYOUT));
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endtask
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class vga_stimulus;
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rand logic [31:0] HWDATA;
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constraint c_hwdata
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{0 <= HWDATA; HWDATA <= 8'h7f;}
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endclass
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vga_stimulus stimulus_vals;
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covergroup cover_vga_chars;
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cp_hwdata: coverpoint vgaif.HWDATA{
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bins invalid = {[128:255]};
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option.auto_bin_max = 128;
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}
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endgroup
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integer char_index;
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string test_value = "";
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initial begin
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cover_vga_chars covvgachars;
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covvgachars = new();
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stimulus_vals = new();
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deassert_reset();
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display_enable = 0;
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@(posedge vgaif.VSYNC);
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display_enable = 1;
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$display(test_value);
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for(char_index = 0; char_index < 16; char_index++)
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begin
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assert (stimulus_vals.randomize) else $fatal;
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setChar(stimulus_vals.HWDATA);
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test_value = {test_value, font_map[stimulus_vals.HWDATA]};
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end
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setChar(8'h08);
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// setChar(8'h54);
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// setChar(8'h45);
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// setChar(8'h53);
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// setChar(8'h54);
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// setChar(8'h21);
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// setChar(8'h00);
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vgaif.HREADY = '0;
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vgaif.HWRITE = '0;
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vgaif.HTRANS = '0;
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vgaif.HSEL = '0;
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vgaif.HADDR = '0;
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vgaif.HWDATA = '0;
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@(posedge vgaif.VSYNC);
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$display(test_value);
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$stop;
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end
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logic rgb_active;
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assign rgb_active = (vgaif.RGB==8'h1c);
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logic checker_rgb_active;
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assign checker_rgb_active = (checker_rgb==8'h1c);
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endmodule
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