supleed2/ELEC70056-HSV-CW2
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About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements
14 commits 1 branch 0 tags 3.8 MiB
SystemVerilog 96.4%
Assembly 3.2%
Tcl 0.2%
Makefile 0.2%
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Alden0012 5c4334ab76 Merge branch 'main' of github.com:supleed2/hsvcw into main
2022-12-12 16:16:23 +00:00
docs Add coursework requirements document 2022-12-02 14:01:20 +00:00
rtl Increase covergroups and test inputs for VGA, Integrate gpio checker in tb 2022-12-12 16:16:17 +00:00
src Initial Commit 2022-11-07 12:41:05 +00:00
tbench Merge branch 'main' of github.com:supleed2/hsvcw into main 2022-12-12 16:16:23 +00:00
ahblite_sys.vc Initial Commit 2022-11-07 12:41:05 +00:00
Makefile Increase covergroups and test inputs for VGA, Integrate gpio checker in tb 2022-12-12 16:16:17 +00:00
readme.txt Initial Commit 2022-11-07 12:41:05 +00:00

readme.txt 

For simulation purposes, place the code.hex file in the same root directory where you launch the Questasim simulation