mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-09-19 20:56:18 +00:00
Fix GPIO assertions and test-bench coverage and constraints
This commit is contained in:
Alden0012
parent
f2b3a72a54
commit
128a2a9eaa
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@ -97,8 +97,10 @@ module AHBGPIO
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// Update input value
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always_ff @(posedge HCLK, negedge HRESETn)
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if(!HRESETn)
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if(!HRESETn) begin
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gpio_datain <= 16'h0000;
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gpio_parityerr <= '0;
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end
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else if (gpio_dir == 16'h0000) begin
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gpio_datain <= GPIOIN[15:0];
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gpio_parityerr <= ~^{GPIOIN,PARITYSEL,INJECT_FAULT};
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@ -111,7 +113,7 @@ module AHBGPIO
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assign PARITYERR = gpio_parityerr;
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//check behaviour
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assert_parity: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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!PARITYERR
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@ -119,23 +121,23 @@ module AHBGPIO
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assert_gpio_write: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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((gpio_dir == 16'h0001)
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&& (HADDR[7:0] == gpio_data_addr)
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((HADDR[7:0] == gpio_data_addr)
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&& HSEL
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&& HWRITE
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&& HTRANS[1])
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|-> (GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
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&& HTRANS[1]
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&& HREADY) |-> ##1
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(gpio_dir == 16'h0001) |-> ##1
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(GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
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);
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assert_gpio_read: assert property
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( @(posedge HCLK) disable iff (!HRESETn)
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((gpio_dir == 16'h0000)
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&& (HADDR[7:0] == gpio_data_addr)
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// && HSEL // HSEL not used in Read always_ff
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&& !HWRITE
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&& HTRANS[1])
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|-> (HRDATA[15:0] == $past(GPIOIN[15:0], 1)
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&& HREADYOUT)
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&& HTRANS[1]
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&& HREADY) |-> ##1
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((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
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);
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assert_gpio_dir: assert property
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@ -143,12 +145,14 @@ module AHBGPIO
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((HADDR[7:0] == gpio_dir_addr)
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&& HSEL
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&& HWRITE
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&& HTRANS[1])
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|-> (gpio_dir == $past(HWDATA[15:0], 1))
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&& HTRANS[1]
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&& HREADY) |-> ##1
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((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
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);
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assume_initial_valid: assume
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( gpio_dir == 16'h0000
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assume_initial_valid: assume property
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( @(posedge HCLK)
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gpio_dir == 16'h0000
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|| gpio_dir == 16'h0001
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);
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@ -1,172 +1,190 @@
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//stub
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interface ahb_gpio_if;
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typedef enum bit[1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQUENTIAL = 2'b10,
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SEQUENTIAL = 2'b11
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} htrans_types;
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typedef enum bit[1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQUENTIAL = 2'b10,
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SEQUENTIAL = 2'b11
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} htrans_types;
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logic HCLK;
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logic HRESETn;
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logic [31:0] HADDR;
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logic [1:0] HTRANS;
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logic [31:0] HWDATA;
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logic HWRITE;
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logic HSEL;
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logic HREADY;
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logic HREADYOUT;
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logic [31:0] HRDATA;
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logic HCLK;
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logic HRESETn;
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logic [31:0] HADDR;
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logic [ 1:0] HTRANS;
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logic [31:0] HWDATA;
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logic HWRITE;
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logic HSEL;
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logic HREADY;
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logic HREADYOUT;
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logic [31:0] HRDATA;
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logic [15:0] GPIOIN;
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logic [15:0] GPIOOUT;
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logic [16:0] GPIOIN;
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logic [16:0] GPIOOUT;
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modport DUT (input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY, GPIOIN,
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output HREADYOUT, HRDATA, GPIOOUT);
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modport DUT
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( input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY, GPIOIN,
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output HREADYOUT, HRDATA, GPIOOUT
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);
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modport TB (input HCLK, HREADYOUT, HRDATA, GPIOOUT,
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output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL, GPIOIN);
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modport TB
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( input HCLK, HREADYOUT, HRDATA, GPIOOUT,
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output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL, GPIOIN
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);
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endinterface
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module ahb_gpio_tb;
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localparam [7:0] gpio_data_addr = 8'h00;
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localparam [7:0] gpio_dir_addr = 8'h04;
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localparam max_test_count = 1000;
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program automatic ahb_gpio_tb
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(ahb_gpio_if.TB gpioif);
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logic parity_sel = '0;
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integer test_count;
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localparam [7:0] gpio_data_addr = 8'h00;
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localparam [7:0] gpio_dir_addr = 8'h04;
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localparam max_test_count = 1000;
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integer test_count;
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ahb_gpio_if gpioif();
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AHBGPIO gpio(
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.HCLK (gpioif.HCLK),
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.HRESETn (gpioif.HRESETn),
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.HADDR (gpioif.HADDR),
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.HTRANS (gpioif.HTRANS),
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.HWDATA (gpioif.HWDATA),
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.HWRITE (gpioif.HWRITE),
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.HSEL (gpioif.HSEL),
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.HREADY (gpioif.HREADY),
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.GPIOIN (gpioif.GPIOIN),
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.PARITYSEL (parity_sel),
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.INJECT_FAULT ('0),
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.HREADYOUT (gpioif.HREADYOUT),
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.HRDATA (gpioif.HRDATA),
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.GPIOOUT (gpioif.GPIOOUT),
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.PARITYERR ()
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);
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class gpio_stimulus;
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typedef enum bit[1:0] {
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GPIO_WRITE = 2'b00,
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GPIO_READ = 2'b01,
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GPIO_DIR = 2'b10,
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RANDOM = 2'b11
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} stimulus_op;
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rand stimulus_op gpio_op;
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class gpio_stimulus;
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rand logic HSEL;
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rand logic HWRITE;
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rand logic HREADY;
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rand logic [ 1:0] HTRANS;
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rand logic [31:0] HWDATA;
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rand logic [31:0] HADDR;
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rand logic [16:0] GPIOIN;
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rand logic HSEL;
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rand logic HWRITE;
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rand logic HREADY;
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rand logic [1:0] HTRANS;
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logic [31:0] prev_haddr = '0;
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rand logic [31:0] HWDATA;
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rand logic [31:0] HADDR;
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rand logic [15:0] GPIOIN;
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constraint c_hsel
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{ HSEL dist { 1 :=99, 0:=1 }; }
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constraint c_hready
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{ HREADY dist { 1 :=99, 0:=1 }; }
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constraint c_htrans
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{ HTRANS dist { 2'b10 :=90, HTRANS :=10};}
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constraint c_haddr
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{ HSEL -> HADDR dist {gpio_data_addr:=40, gpio_dir_addr:=40, HADDR:=20};}
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constraint c_gpio_dir_write
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{
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(prev_haddr[7:0]==gpio_dir_addr) -> (HWDATA==32'h0000 || HWDATA ==32'h0001);
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}
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constraint c_gpioin_parity
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{ GPIOIN[16] == ~^{GPIOIN[15:0],parity_sel};}
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constraint c_haddr {((gpio_op == GPIO_WRITE) && (HADDR == gpio_data_addr)) ||
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((gpio_op == GPIO_DIR) && (HADDR == gpio_dir_addr)) ||
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(gpio_op == GPIO_READ) ||
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(gpio_op == RANDOM);}
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function void post_randomize;
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prev_haddr = HADDR;
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endfunction
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endclass
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constraint c_write {((gpio_op == GPIO_WRITE)|| (gpio_op == GPIO_DIR)) -> (HSEL && HWRITE && HREADY && (HTRANS == 2'b10));}
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gpio_stimulus stimulus_vals;
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constraint c_read {(gpio_op == GPIO_READ) -> (HSEL && !HWRITE && HREADY);}
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endclass
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covergroup cover_ahb_transaction_vals;
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cp_hsel: coverpoint gpioif.HSEL{
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bins hi = {1};
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bins lo = {0};
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}
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cp_hready: coverpoint gpioif.HREADY{
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bins hi = {1};
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bins lo = {0};
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}
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cp_hwrite: coverpoint gpioif.HWRITE{
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bins write = {1};
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bins read = {0};
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}
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cp_haddr: coverpoint gpioif.HADDR {
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bins data_addr = {gpio_data_addr};
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bins dir_addr = {gpio_dir_addr};
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bins invalid_addr = default;
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}
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cp_ahb_transaction: cross cp_hsel, cp_hready, cp_hwrite, cp_haddr {
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bins ahb_write = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==1 && cp_haddr==gpio_data_addr);
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bins ahb_read = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==0);
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bins ahb_dir = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==1 && cp_haddr==gpio_dir_addr);
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ignore_bins ignore_invalid = cp_ahb_transaction with (cp_hsel!=1);
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}
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gpio_stimulus stimulus_vals;
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endgroup
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covergroup cover_addr_values;
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coverpoint gpioif.HADDR {
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bins data_addr = {gpio_data_addr};
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bins dir_addr = {gpio_dir_addr};
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bins invalid_addr = default;
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}
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endgroup
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covergroup cover_ahb_write_values;
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coverpoint gpioif.HWDATA;
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endgroup
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covergroup cover_wr_vals;
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coverpoint {HSEL,HWRITE,HREADY} {
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bins write = {{1,1,1}};
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bins read = {{1,0,1}};
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bins invalid = default;
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}
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endgroup
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covergroup cover_ahb_read_values;
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coverpoint gpioif.HRDATA;
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endgroup
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covergroup cover_ahb_write_values;
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coverpoint gpioif.HWDATA {
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bins zero = {0};
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bins lo = {[1:7]};
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bins med = {[8:23]};
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bins hi = {[24:30]};
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bins max = {32'hFFFF};
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}
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endgroup
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covergroup cover_gpio_in_values;
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coverpoint gpioif.GPIOIN;
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endgroup
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covergroup cover_ahb_read_values;
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coverpoint gpioif.HRDATA {
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bins zero = {0};
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bins lo = {[1:7]};
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bins med = {[8:23]};
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bins hi = {[24:30]};
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bins max = {32'hFFFF};
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}
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endgroup
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covergroup cover_gpio_out_values;
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coverpoint gpioif.GPIOOUT;
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endgroup
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covergroup cover_gpio_in_values;
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coverpoint gpioif.GPIOIN {
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bins zero = {0};
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bins lo = {[1:4]};
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bins med = {[5:9]};
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bins high = {[10:14]};
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bins max = {16'hFF};
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}
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endgroup
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task deassert_reset();
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begin
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gpioif.HRESETn = 0;
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@(posedge gpioif.HCLK);
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@(posedge gpioif.HCLK);
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gpioif.HRESETn = 1;
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end
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endtask
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covergroup cover_gpio_out_values;
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coverpoint gpioif.GPIOOUT {
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bins zero = {0};
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bins lo = {[1:4]};
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bins med = {[5:9]};
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bins high = {[10:14]};
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bins max = {16'hFF};
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}
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endgroup
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task deassert_reset();
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begin
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gpioif.HRESETn = 0;
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@(posedge gpioif.HCLK);
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@(posedge gpioif.HCLK);
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gpioif.HRESETn = 1;
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@(posedge gpioif.HCLK);
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end
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endtask
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initial begin
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cover_ahb_write_values covahbwrite;
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cover_ahb_read_values covahbread;
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cover_gpio_in_values covgpioin;
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cover_gpio_out_values covgpioout;
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cover_ahb_transaction_vals covahbtransactionvals;
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covahbwrite = new();
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covahbread = new();
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covgpioin = new();
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covgpioout = new();
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covahbtransactionvals = new();
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stimulus_vals = new();
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deassert_reset();
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initial begin
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cover_addr_values covaddr;
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cover_ahb_write_values covahbwrite;
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cover_ahb_read_values covahbread;
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cover_gpio_in_values covgpioin;
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cover_gpio_out_values covgpioout;
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covaddr = new();
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covahbwrite = new();
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covahbread = new();
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covgpioin = new();
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covgpioout = new();
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for(test_count = 0; test_count < max_test_count;test_count++)
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begin
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assert (stimulus_vals.randomize) else $fatal;
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gpioif.HSEL = stimulus_vals.HSEL;
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gpioif.HWRITE = stimulus_vals.HWRITE;
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gpioif.HREADY = stimulus_vals.HREADY;
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gpioif.HTRANS = stimulus_vals.HTRANS;
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gpioif.HWDATA = stimulus_vals.HWDATA;
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gpioif.HADDR = stimulus_vals.HADDR;
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gpioif.GPIOIN = stimulus_vals.GPIOIN;
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deassert_reset();
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covahbwrite.sample();
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covgpioin.sample();
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covahbread.sample();
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covgpioout.sample();
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for(test_count = 0; test_count < max_test_count;test_count++)
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begin
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@(posedge gpioif.HCLK);
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assert (stimulus_vals.randomize) else $fatal;
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gpioif.HSEL = stimulus_vals.HSEL;
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gpioif.HWRITE = stimulus_vals.HWRITE;
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gpioif.HREADY = stimulus_vals.HREADY;
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gpioif.HTRANS = stimulus_vals.HTRANS;
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gpioif.HWDATA = stimulus_vals.HWDATA;
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gpioif.HADDR = stimulus_vals.HADDR;
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gpioif.GPIOIN = stimulus_vals.GPIOIN;
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covahbtransactionvals.sample();
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covaddr.sample();
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covahbwrite.sample();
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covgpioin.sample();
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covahbread.sample();
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covgpioout.sample();
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end
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@(posedge gpioif.HCLK);
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$finish;
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end
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endprogram
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@(posedge gpioif.HCLK);
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end
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@(posedge gpioif.HCLK);
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$finish;
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end
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initial begin
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gpioif.HCLK = 0;
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forever #1 gpioif.HCLK = ! gpioif.HCLK;
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end
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endmodule
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