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Add parity generation and checking to AHBGPIO.sv

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Aadi Desai 2022-11-07 13:36:56 +00:00
parent c83b8a73f1
commit 018013d3c8
1 changed files with 40 additions and 49 deletions
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89
rtl/AHB_GPIO/AHBGPIO.sv
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@ -3,7 +3,7 @@
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//THIS END USER LICENCE AGREEMENT (<EFBFBD>LICENCE<EFBFBD>) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
@ -35,90 +35,81 @@
//////////////////////////////////////////////////////////////////////////////////
module AHBGPIO(
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
input wire [15:0] GPIOIN,
module AHBGPIO
( input wire HCLK
, input wire HRESETn
, input wire [31:0] HADDR
, input wire [1:0] HTRANS
, input wire [31:0] HWDATA
, input wire HWRITE
, input wire HSEL
, input wire HREADY
, input wire [16:0] GPIOIN
, input wire PARITYSEL
, input wire INJECT_FAULT
//Output
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [15:0] GPIOOUT
);
, output wire HREADYOUT
, output wire [31:0] HRDATA
, output wire [16:0] GPIOOUT
, output wire PARITYERR
);
localparam [7:0] gpio_data_addr = 8'h00;
localparam [7:0] gpio_dir_addr = 8'h04;
reg [15:0] gpio_dataout;
reg gpio_parityout;
reg [15:0] gpio_datain;
reg gpio_parityerr;
reg [15:0] gpio_dir;
reg [15:0] gpio_data_next;
reg [31:0] last_HADDR;
reg [1:0] last_HTRANS;
reg last_HWRITE;
reg last_HSEL;
integer i;
assign HREADYOUT = 1'b1;
// Set Registers from address phase
// Set Registers from address phase
always @(posedge HCLK)
begin
if(HREADY)
begin
if(HREADY) begin
last_HADDR <= HADDR;
last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
end
end
// Update in/out switch
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_dir <= 16'h0000;
end
else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dir <= HWDATA[15:0];
end
// Update output value
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_dataout <= 16'h0000;
end
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
{gpio_parityout, gpio_dataout} <= 17'd0;
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) begin
gpio_dataout <= HWDATA[15:0];
end
gpio_parityout <= ~^{HWDATA[15:0],PARITYSEL,INJECT_FAULT};
end
// Update input value
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_datain <= 16'h0000;
else if (gpio_dir == 16'h0000) begin
gpio_datain <= GPIOIN[15:0];
gpio_parityerr <= ~^{GPIOIN,PARITYSEL,INJECT_FAULT};
end
else if (gpio_dir == 16'h0000)
gpio_datain <= GPIOIN;
else if (gpio_dir == 16'h0001)
gpio_datain <= GPIOOUT;
end
assign HRDATA[15:0] = gpio_datain;
assign GPIOOUT = gpio_dataout;
assign HRDATA[15:0] = gpio_datain;
assign GPIOOUT = {gpio_parityout, gpio_dataout};
assign PARITYERR = gpio_parityerr;
endmodule