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https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-12-22 13:45:49 +00:00
Add redundant VGA and comparator module
This commit is contained in:
Alden0012
parent
4edfce0e03
commit
f50d0c5c2e
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@ -38,30 +38,31 @@
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module AHBLITE_SYS(
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//CLOCKS & RESET
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input wire CLK,
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input wire RESET,
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input wire RESET,
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//TO BOARD LEDs
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output wire [7:0] LED,
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// Switch Inputs
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input wire [7:0] SW,
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//VGA IO
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output wire [2:0] VGARED,
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output wire [2:0] VGAGREEN,
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output wire [1:0] VGABLUE,
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output wire HSYNC, //VGA Horizontal Sync
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output wire VSYNC, //VGA Vertical Sync
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// Debug
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input wire TCK_SWCLK, // SWD Clk / JTAG TCK
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input wire TDI_NC, // NC / JTAG TDI
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inout wire TMS_SWDIO, // SWD I/O / JTAG TMS
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output wire TDO_SWO // SW Out / JTAG TDO
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output wire TDO_SWO, // SW Out / JTAG TDO
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output wire VGA_MISMATCH
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);
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//AHB-LITE SIGNALS
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//AHB-LITE SIGNALS
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//Global Signals
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wire HCLK;
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wire HRESETn;
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@ -82,19 +83,19 @@ wire HREADY;
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//SELECT SIGNALS
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wire [3:0] MUX_SEL;
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wire HSEL_MEM;
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wire HSEL_GPIO;
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wire HSEL_VGA;
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//SLAVE READ DATA
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wire [31:0] HRDATA_MEM;
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wire [31:0] HRDATA_GPIO;
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wire [31:0] HRDATA_VGA;
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//SLAVE HREADYOUT
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wire HREADYOUT_MEM;
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wire HREADYOUT_GPIO;
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wire HREADYOUT_VGA;
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wire HSEL_MEM;
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wire HSEL_GPIO;
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wire HSEL_VGA;
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//SLAVE READ DATA
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wire [31:0] HRDATA_MEM;
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wire [31:0] HRDATA_GPIO;
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wire [31:0] HRDATA_VGA;
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//SLAVE HREADYOUT
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wire HREADYOUT_MEM;
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wire HREADYOUT_GPIO;
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wire HREADYOUT_VGA;
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//CM0-DS Sideband signals
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wire [31:0] IRQ;
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@ -104,6 +105,15 @@ wire lockup;
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wire lockup_reset_req;
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wire sys_reset_req;
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// VGA Redundant Signals
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wire [31:0] HRDATA_VGA_2;
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wire HREADYOUT_VGA_2;
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wire HSYNC_2;
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wire VSYNC_2;
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wire [2:0] VGARED_2,
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wire [2:0] VGAGREEN_2,
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wire [1:0] VGABLUE_2,
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//SYSTEM GENERATES NO ERROR RESPONSE
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assign HRESP = 1'b0;
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@ -115,14 +125,14 @@ wire fclk; // Free running clock
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// Reset
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wire reset_n = RESET;
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// Clock divider, divide the frequency by two, hence less time constraint
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// Clock divider, divide the frequency by two, hence less time constraint
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reg clk_div;
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always @(posedge CLK)
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begin
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clk_div=~clk_div;
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end
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assign fclk = clk_div;
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assign fclk = clk_div;
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// Reset synchronizer
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reg [4:0] reset_sync_reg;
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@ -228,11 +238,11 @@ CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION (
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.RSTBYPASS (1'b0)
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);
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//Address Decoder
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//Address Decoder
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AHBDCD uAHBDCD (
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.HADDR(HADDR[31:0]),
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.HSEL_S0(HSEL_MEM),
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.HSEL_S1(HSEL_VGA),
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.HSEL_S2(),
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@ -244,7 +254,7 @@ AHBDCD uAHBDCD (
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.HSEL_S8(),
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.HSEL_S9(),
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.HSEL_NOMAP(),
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.MUX_SEL(MUX_SEL[3:0])
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);
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@ -254,7 +264,7 @@ AHBMUX uAHBMUX (
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.MUX_SEL(MUX_SEL[3:0]),
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.HRDATA_S0(HRDATA_MEM),
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.HRDATA_S1(HRDATA_VGA),
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.HRDATA_S2(32'h00000000),
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@ -266,7 +276,7 @@ AHBMUX uAHBMUX (
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.HRDATA_S8(32'h00000000),
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.HRDATA_S9(32'h00000000),
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.HRDATA_NOMAP(32'hDEADBEEF),
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.HREADYOUT_S0(HREADYOUT_MEM),
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.HREADYOUT_S1(HREADYOUT_VGA),
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.HREADYOUT_S2(1'b1),
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@ -278,7 +288,7 @@ AHBMUX uAHBMUX (
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.HREADYOUT_S8(1'b1),
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.HREADYOUT_S9(1'b1),
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.HREADYOUT_NOMAP(1'b1),
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.HRDATA(HRDATA[31:0]),
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.HREADY(HREADY)
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);
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@ -290,37 +300,68 @@ AHBMUX uAHBMUX (
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AHB2MEM uAHB2MEM (
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//AHBLITE Signals
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.HSEL(HSEL_MEM),
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HREADY(HREADY),
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HREADY(HREADY),
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.HADDR(HADDR),
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.HTRANS(HTRANS[1:0]),
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.HTRANS(HTRANS[1:0]),
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.HWRITE(HWRITE),
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.HSIZE(HSIZE),
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.HWDATA(HWDATA[31:0]),
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.HRDATA(HRDATA_MEM),
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.HWDATA(HWDATA[31:0]),
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.HRDATA(HRDATA_MEM),
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.HREADYOUT(HREADYOUT_MEM)
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);
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// AHBLite VGA Peripheral
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AHBVGA uAHBVGA (
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HREADY(HREADY),
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.HWRITE(HWRITE),
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.HTRANS(HTRANS),
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.HSEL(HSEL_VGA),
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.HRDATA(HRDATA_VGA),
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.HREADYOUT(HREADYOUT_VGA),
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.HSYNC(HSYNC),
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.VSYNC(VSYNC),
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HREADY(HREADY),
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.HWRITE(HWRITE),
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.HTRANS(HTRANS),
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.HSEL(HSEL_VGA),
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.HRDATA(HRDATA_VGA),
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.HREADYOUT(HREADYOUT_VGA),
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.HSYNC(HSYNC),
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.VSYNC(VSYNC),
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.RGB({VGARED,VGAGREEN,VGABLUE})
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);
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);
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// AHBLite GPIO
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// AHBLite VGA Peripheral (Redundant)
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AHBVGA uAHBVGA2 (
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HREADY(HREADY),
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.HWRITE(HWRITE),
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.HTRANS(HTRANS),
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.HSEL(HSEL_VGA),
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.HRDATA(HRDATA_VGA_2),
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.HREADYOUT(HREADYOUT_VGA_2),
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.HSYNC(HSYNC_2),
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.VSYNC(VSYNC_2),
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.RGB({VGARED_2,VGAGREEN_2,VGABLUE_2})
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);
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VGACOMPARATOR uVGACOMPARATOR (
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.HRDATA1 (HRDATA_VGA),
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.HREADYOUT1 (HREADYOUT_VGA),
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.HSYNC1 (HSYNC),
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.VSYNC1 (VSYNC),
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.RGB1 ({VGARED,VGAGREEN,VGABLUE}),
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.HRDATA2 (HRDATA_VGA_2),
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.HREADYOUT2 (HREADYOUT_VGA_2),
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.HSYNC2 (HSYNC_2),
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.VSYNC2 (VSYNC_2),
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.RGB2 ({VGARED_2,VGAGREEN_2,VGABLUE_2}),
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.MISMATCH (VGA_MISMATCH)
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);
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// AHBLite GPIO
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AHBGPIO uAHBGPIO(
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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@ -333,9 +374,9 @@ AHBGPIO uAHBGPIO(
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.HSEL(HSEL_GPIO),
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.HRDATA(HRDATA_GPIO),
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.HREADYOUT(HREADYOUT_GPIO),
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.GPIOIN({8'b00000000,SW[7:0]}),
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.GPIOOUT(LED[7:0])
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);
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endmodule
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23
rtl/AHB_VGA/VGACOMPARATOR.sv
Normal file
23
rtl/AHB_VGA/VGACOMPARATOR.sv
Normal file
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@ -0,0 +1,23 @@
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module VGACOMPARATOR
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( input logic [31:0] HRDATA1
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, input logic HREADYOUT1
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, input logic HSYNC1
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, input logic VSYNC1
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, input logic [ 7:0] RGB1
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, input logic [31:0] HRDATA2
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, input logic HREADYOUT2
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, input logic HSYNC2
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, input logic VSYNC2
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, input logic [ 7:0] RGB2
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, output logic MISMATCH
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);
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assign MISMATCH =
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!( HRDATA1 == HRDATA2
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&& HREADYOUT1 == HREADYOUT2
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&& HSYNC1 == HSYNC2
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&& VSYNC1 == VSYNC2
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&& RGB1 == RGB2
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)
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endmodule
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