supleed2/ELEC70056-HSV-CW2
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  • 5c8daf3ea0 Add fixes and documentation main Aadi Desai 2022-12-16 22:16:17 +0000
  • 8ae5a07fca add updated vga files Alden0012 2022-12-16 22:11:31 +0000
  • 3c60629d48 Add scripts/rtl for formal verification Alden0012 2022-12-16 20:19:07 +0000
  • 827ed444fa Fixes and adding missing setup.do script for vsim Aadi Desai 2022-12-12 16:49:07 +0000
  • 5c4334ab76 Merge branch 'main' of github.com:supleed2/hsvcw into main Alden0012 2022-12-12 16:16:23 +0000
  • aabd220e6a Increase covergroups and test inputs for VGA, Integrate gpio checker in tb Alden0012 2022-12-12 16:16:17 +0000
  • 9c9536016b Format top tb and add vga image buffer reset task Aadi Desai 2022-12-12 16:05:01 +0000
  • f586cd95d9 Add VGA and GPIO checker Alden0012 2022-12-05 16:55:23 +0000
  • f9bd753cde Add coursework requirements document Aadi Desai 2022-12-02 14:01:20 +0000
  • 128a2a9eaa Fix GPIO assertions and test-bench coverage and constraints Alden0012 2022-11-14 15:28:45 +0000
  • f2b3a72a54 Add initial GPIO test-bench Alden0012 2022-11-14 10:24:11 +0000
  • f50d0c5c2e Add redundant VGA and comparator module Alden0012 2022-11-08 17:49:23 +0000
  • 4edfce0e03 Add initial assume to AHBGPIO.sv Alden0012 2022-11-08 17:27:39 +0000
  • 0f8578e1b8 Add assertions to AHBGPIO.sv Alden0012 2022-11-08 17:04:59 +0000
  • 0d4099ce15 Update AHBVGASYS.sv to SystemVerilog and style Aadi Desai 2022-11-07 13:57:19 +0000
  • 018013d3c8 Add parity generation and checking to AHBGPIO.sv Aadi Desai 2022-11-07 13:36:56 +0000
  • c83b8a73f1 Switch all Verilog files to SystemVerilog file endings Aadi Desai 2022-11-07 12:58:43 +0000
  • dcdda4d9e1 Initial Commit Aadi Desai 2022-11-07 12:41:05 +0000