supleed2/ELEC70056-HSV-CW2
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About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements
17 commits 1 branch 0 tags 3.8 MiB
SystemVerilog 96.4%
Assembly 3.2%
Tcl 0.2%
Makefile 0.2%
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Alden0012 8ae5a07fca add updated vga files
2022-12-16 22:11:31 +00:00
coverage Add scripts/rtl for formal verification 2022-12-16 20:19:07 +00:00
docs Add coursework requirements document 2022-12-02 14:01:20 +00:00
rtl add updated vga files 2022-12-16 22:11:31 +00:00
src Initial Commit 2022-11-07 12:41:05 +00:00
tbench Add scripts/rtl for formal verification 2022-12-16 20:19:07 +00:00
ahblite_sys.vc Initial Commit 2022-11-07 12:41:05 +00:00
gpio.tcl Add scripts/rtl for formal verification 2022-12-16 20:19:07 +00:00
Makefile Increase covergroups and test inputs for VGA, Integrate gpio checker in tb 2022-12-12 16:16:17 +00:00
readme.txt Initial Commit 2022-11-07 12:41:05 +00:00
setup.do Fixes and adding missing setup.do script for vsim 2022-12-12 16:49:07 +00:00
vga.tcl Add scripts/rtl for formal verification 2022-12-16 20:19:07 +00:00

readme.txt 

For simulation purposes, place the code.hex file in the same root directory where you launch the Questasim simulation