supleed2/ELEC40006-P1-CW
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Author SHA1 Message Date
Benjamin aff07036e0 Fixed multiplier bug 2020-06-13 01:41:24 +01:00
Aadi Desai 87f3d0e919 CPU set up for testing and analysis 2020-06-11 17:28:00 +01:00
Aadi Desai 6c1f7fc59b Remove debug lines from ALU to improve performance 2020-06-11 16:23:16 +01:00
Benjamin Ramhorst d6bb9bd762 Added infrastructure for Fibonacci's number 2020-06-10 20:10:34 +01:00
Benjamin Ramhorst 3e4e5569b1 Added testing for Fibonacci and linked list 2020-06-10 18:01:31 +01:00
Aadi Desai 4688a56452 Modified Test Program to add LDR and STR 
Also fixed logic within decoder for LDR and STR
 2020-06-10 15:51:51 +01:00
Kacper 719c9ede2b Added decoder logic for STR and LDR 2020-06-10 14:40:58 +01:00
Aadi Desai a1cf89e644 Added LDR and STR to alu and set up data paths 
Decoder changes remaining
 2020-06-10 14:02:15 +01:00
Kacper a249245102 Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-10 13:00:43 +01:00
Kacper 6839781fa0 Added STR and LDR to the cpp generator 2020-06-10 13:00:40 +01:00
Aadi Desai d046242bc1 Final State before Pipelining 
Debug Complete, data and instruction mifs + ram files. Test program checked
 2020-06-09 22:45:20 +01:00
Aadi Desai 7a02c2c234
Merge pull request #1 from supleed2/alu 
Alu MUL, MLA and MLS fixed. LUT in multiply block fixed.
 2020-06-09 20:35:41 +01:00
Aadi Desai fefcad13ce Updated alu to feed only positive values to multiply block 
When both values are positive/negative the positive result from the multiply block is correct. When only one is negative, the result is inverted.
 2020-06-09 20:34:29 +01:00
Aadi Desai 12da9b94a5 Updated LUT to have an unregistered output 
Allows Multiply block output to be valid after 1 clock cycle rather than 2
 2020-06-09 20:33:10 +01:00
Kacper 20f2adc4a1 Removed some waveform and test files 2020-06-09 19:01:55 +01:00
Kacper 46282576df Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
Kacper 778dd7f538 Update test_no_mul.txt 2020-06-09 12:11:06 +01:00
Kacper 7b6806967d Update data.mif 2020-06-08 23:08:11 +01:00
Kacper 2f6cbeae56 Debugging complete! 
The CPU works now except for the multiply commands. Pipelining is next! Woooo!
 2020-06-08 23:07:52 +01:00
Kacper c2ce212ed5 Fixed ASR in C++ generator 2020-06-08 21:37:12 +01:00
Kacper 47f20744ac Added new test mif with no multiplication 2020-06-08 13:13:26 +01:00
Kacper 24b293e24b Recompiled certain files 2020-06-08 12:10:14 +01:00
Kacper 8272afe500 Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-07 23:23:20 +01:00
Kacper 3d9ea175cd Working on debugging 
The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.
 2020-06-07 23:23:13 +01:00
Kacper 64ca41b287 Resolved ISA conflict 2020-06-07 22:35:29 +01:00
Kacper b527d5e77d Debugging CPU 2020-06-07 20:51:33 +01:00
Aadi Desai 94124c5a0e
Update LIFOstack to support 32 memory slots 
Also fixed typo on line 15, previous version had a pointer for 16 slots but the memory register only had 4 slots
 2020-06-07 20:05:46 +01:00
Kacper 42739283f5 Update .gitignore 2020-06-07 17:45:40 +01:00
Kacper 24e22f13ec Fixed instrGen and added large test 
Also added a note about the OR instruction. Either to fix later or leave as is.
 2020-06-07 17:41:37 +01:00
Kacper 0b1ffea9ce Updated instruction generator to include new opcodes 2020-06-07 17:10:37 +01:00
Kacper 9a1a1da664 Complete CPU v2 (not tested) 2020-06-07 16:12:05 +01:00
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Aadi Desai f6b3489884 Updated ALU to include PSH and POP 2020-06-04 18:12:24 +01:00
Aadi Desai 7997617e00 Add stack Verilog file 
Uses Last In First Out ordering
 2020-06-04 18:03:46 +01:00
Kacper 4318a5b70b CPU completed 2020-06-04 16:33:27 +01:00
Aadi Desai 12bd671c00 Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-04 15:05:17 +01:00
Aadi Desai 08a8635959 Updated ALU to use internal carry register 
Also tidied up begin/end tags to reduce number of lines and improve readability
 2020-06-04 15:05:13 +01:00
Benjamin Ramhorst f8edff65a1 Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-04 00:36:27 +01:00
Benjamin Ramhorst 09dd851499 Completed source code for generating .mif files from opcodes and registers 2020-06-04 00:36:11 +01:00
Aadi Desai 3647e0b15c ALU now uses multiply block rather than * operator 
Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input
 2020-06-03 15:15:44 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Aadi Desai e1d7bf884d Merge branch 'master' of https://github.com/supleed2/CPUProject 2020-06-02 16:58:04 +01:00
Aadi Desai 2ca1e90a2c ALU enable control added, minor fix with RRC 
Multiply still to be updated
 2020-06-02 16:57:58 +01:00
ben 5d6c9803fc Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
Aadi Desai 3f0c91b0ff
Initial ALU Verilog 
Currently using incorrect implementation for Multiply (* operator), to be fixed once Multiply method is decided
 2020-05-29 14:16:02 +01:00
Benjamin Ramhorst fedfcaaada
Added most of the code for generating the instruction MIF. Still need to do a big if-else statement for every instruction. 2020-05-28 14:42:02 -07:00
ben 3d6e456fcc Almost completed 16 bit multiplier. 2020-05-28 15:02:22 -07:00
ben e39d2f653a Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
Kacper 132e1ad7fe
Delete DECODE.v.bak 2020-05-27 18:59:12 +01:00
Kacper cf179ad2cf Revisions for testing 2020-05-27 18:53:59 +01:00