mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
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Final State before Pipelining
Debug Complete, data and instruction mifs + ram files. Test program checked
This commit is contained in:
parent
7a02c2c234
commit
d046242bc1
477
ALU_top.bdf
477
ALU_top.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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||||
*/
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/*
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||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
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||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
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||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
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||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
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||||
|
|
@ -16,142 +16,143 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
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||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 240 528 256)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "ALU_en" (rect 5 0 43 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(rect 352 240 528 256)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "ALU_en" (rect 9 0 47 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 256 528 272)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "Rs1[15..0]" (rect 5 0 52 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(rect 352 256 528 272)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "Rs1[15..0]" (rect 9 0 60 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 272 528 288)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "Rs2[15..0]" (rect 5 0 52 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(rect 352 272 528 288)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "Rs2[15..0]" (rect 9 0 60 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 288 528 304)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "Rd[15..0]" (rect 5 0 47 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(rect 352 288 528 304)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "Rd[15..0]" (rect 9 0 55 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 304 528 320)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "op[5..0]" (rect 5 0 40 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(rect 352 304 528 320)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "op[5..0]" (rect 9 0 46 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 360 336 528 352)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "EXEC2" (rect 5 0 36 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(rect 352 336 528 352)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "EXEC2" (rect 9 0 43 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 336 448 504 464)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "CLK" (rect 5 0 26 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(rect 344 448 520 464)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "CLK" (rect 9 0 30 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 336 352 520 368)
|
||||
(text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6)))
|
||||
(text "stack_data[15..0]" (rect 5 0 92 12)(font "Arial" ))
|
||||
(pt 184 8)
|
||||
(rect 352 352 528 368)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "stack_data[15..0]" (rect 9 0 95 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 100 12)(pt 125 12))
|
||||
(line (pt 100 4)(pt 125 4))
|
||||
(line (pt 129 8)(pt 184 8))
|
||||
(line (pt 100 12)(pt 100 4))
|
||||
(line (pt 125 4)(pt 129 8))
|
||||
(line (pt 125 12)(pt 129 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 776 272 952 288)
|
||||
(rect 784 272 960 288)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "Rout[15..0]" (rect 90 0 141 17)(font "Intel Clear" ))
|
||||
(text "Rout[15..0]" (rect 90 0 145 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
|
|
@ -165,7 +166,7 @@ refer to the applicable agreement for further details.
|
|||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 776 288 952 304)
|
||||
(rect 784 288 960 304)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "COND" (rect 90 0 123 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
|
|
@ -181,7 +182,7 @@ refer to the applicable agreement for further details.
|
|||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 776 304 952 320)
|
||||
(rect 784 304 960 320)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "CARRY" (rect 90 0 130 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
|
|
@ -211,6 +212,54 @@ refer to the applicable agreement for further details.
|
|||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 784 320 960 336)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "jumpflags[7..0]" (rect 90 0 164 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 784 240 960 256)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "mul1[15..0]" (rect 90 0 145 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 784 256 960 272)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "mul2[15..0]" (rect 90 0 144 17)(font "Intel Clear" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 544 424 744 520)
|
||||
(text "mul16" (rect 5 0 43 19)(font "Intel Clear" (font_size 8)))
|
||||
|
|
@ -248,7 +297,7 @@ refer to the applicable agreement for further details.
|
|||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 544 216 752 392)
|
||||
(rect 544 216 760 392)
|
||||
(text "alu" (rect 5 0 19 12)(font "Arial" ))
|
||||
(text "ALU_in" (rect 8 160 43 172)(font "Arial" ))
|
||||
(port
|
||||
|
|
@ -308,42 +357,49 @@ refer to the applicable agreement for further details.
|
|||
(line (pt 0 144)(pt 16 144)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 32)
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 55 12)(font "Arial" ))
|
||||
(text "mul1[15..0]" (rect 141 27 187 39)(font "Arial" ))
|
||||
(line (pt 208 32)(pt 192 32)(line_width 3))
|
||||
(text "mul1[15..0]" (rect 149 27 204 39)(font "Arial" ))
|
||||
(line (pt 216 32)(pt 200 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 48)
|
||||
(pt 216 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 55 12)(font "Arial" ))
|
||||
(text "mul2[15..0]" (rect 141 43 187 55)(font "Arial" ))
|
||||
(line (pt 208 48)(pt 192 48)(line_width 3))
|
||||
(text "mul2[15..0]" (rect 149 43 204 55)(font "Arial" ))
|
||||
(line (pt 216 48)(pt 200 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 64)
|
||||
(pt 216 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 55 12)(font "Arial" ))
|
||||
(text "Rout[15..0]" (rect 141 59 187 71)(font "Arial" ))
|
||||
(line (pt 208 64)(pt 192 64)(line_width 3))
|
||||
(text "Rout[15..0]" (rect 149 59 204 71)(font "Arial" ))
|
||||
(line (pt 216 64)(pt 200 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 80)
|
||||
(pt 216 80)
|
||||
(output)
|
||||
(text "jump" (rect 0 0 23 12)(font "Arial" ))
|
||||
(text "jump" (rect 168 75 187 87)(font "Arial" ))
|
||||
(line (pt 208 80)(pt 192 80))
|
||||
(text "jump" (rect 176 75 199 87)(font "Arial" ))
|
||||
(line (pt 216 80)(pt 200 80))
|
||||
)
|
||||
(port
|
||||
(pt 208 96)
|
||||
(pt 216 96)
|
||||
(output)
|
||||
(text "carry" (rect 0 0 25 12)(font "Arial" ))
|
||||
(text "carry" (rect 166 91 187 103)(font "Arial" ))
|
||||
(line (pt 208 96)(pt 192 96))
|
||||
(text "carry" (rect 174 91 199 103)(font "Arial" ))
|
||||
(line (pt 216 96)(pt 200 96))
|
||||
)
|
||||
(port
|
||||
(pt 216 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 74 12)(font "Arial" ))
|
||||
(text "jumpflags[7..0]" (rect 133 107 207 119)(font "Arial" ))
|
||||
(line (pt 216 112)(pt 200 112)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 192 160))
|
||||
(rectangle (rect 16 16 200 160))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
|
|
@ -371,101 +427,11 @@ refer to the applicable agreement for further details.
|
|||
(pt 536 472)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 536 416)
|
||||
(pt 768 416)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 248)
|
||||
(pt 528 248)
|
||||
)
|
||||
(connector
|
||||
(pt 544 264)
|
||||
(pt 528 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 280)
|
||||
(pt 528 280)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 296)
|
||||
(pt 528 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 312)
|
||||
(pt 528 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 536 400)
|
||||
(pt 536 328)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 752 400)
|
||||
(pt 536 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 536 328)
|
||||
(pt 544 328)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 344)
|
||||
(pt 528 344)
|
||||
)
|
||||
(connector
|
||||
(pt 752 264)
|
||||
(pt 760 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 760 408)
|
||||
(pt 760 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 408)
|
||||
(pt 760 408)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 768 248)
|
||||
(pt 752 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 768 416)
|
||||
(pt 768 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 752 280)
|
||||
(pt 776 280)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 752 296)
|
||||
(pt 776 296)
|
||||
)
|
||||
(connector
|
||||
(pt 752 312)
|
||||
(pt 776 312)
|
||||
)
|
||||
(connector
|
||||
(pt 544 456)
|
||||
(pt 504 456)
|
||||
)
|
||||
(connector
|
||||
(pt 544 360)
|
||||
(pt 520 360)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 744 456)
|
||||
(pt 752 456)
|
||||
|
|
@ -476,4 +442,111 @@ refer to the applicable agreement for further details.
|
|||
(pt 768 456)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 344)
|
||||
(pt 544 344)
|
||||
)
|
||||
(connector
|
||||
(pt 544 360)
|
||||
(pt 528 360)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 328)
|
||||
(pt 536 328)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 536 400)
|
||||
(pt 536 328)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 248)
|
||||
(pt 544 248)
|
||||
)
|
||||
(connector
|
||||
(pt 528 264)
|
||||
(pt 544 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 280)
|
||||
(pt 544 280)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 296)
|
||||
(pt 544 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 312)
|
||||
(pt 544 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 544 456)
|
||||
(pt 520 456)
|
||||
)
|
||||
(connector
|
||||
(pt 760 280)
|
||||
(pt 784 280)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 760 296)
|
||||
(pt 784 296)
|
||||
)
|
||||
(connector
|
||||
(pt 760 312)
|
||||
(pt 784 312)
|
||||
)
|
||||
(connector
|
||||
(pt 536 416)
|
||||
(pt 776 416)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 776 416)
|
||||
(pt 776 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 528 408)
|
||||
(pt 768 408)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 768 264)
|
||||
(pt 768 408)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 760 328)
|
||||
(pt 784 328)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 760 264)
|
||||
(pt 768 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 768 264)
|
||||
(pt 784 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 760 248)
|
||||
(pt 776 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 776 248)
|
||||
(pt 784 248)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 752 456))
|
||||
(junction (pt 768 264))
|
||||
(junction (pt 776 248))
|
||||
|
|
|
|||
48
ALU_top.bsf
48
ALU_top.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
|
|
@ -82,30 +83,51 @@ refer to the applicable agreement for further details.
|
|||
(port
|
||||
(pt 248 32)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rout[15..0]" (rect 161 27 227 46)(font "Intel Clear" (font_size 8)))
|
||||
(text "mul1[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "mul1[15..0]" (rect 158 27 227 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 32)(pt 232 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 48)
|
||||
(output)
|
||||
(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "COND" (rect 191 43 227 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 48)(pt 232 48))
|
||||
(text "mul2[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "mul2[15..0]" (rect 158 43 227 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 48)(pt 232 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 64)
|
||||
(output)
|
||||
(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CARRY" (rect 186 59 227 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 64)(pt 232 64))
|
||||
(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rout[15..0]" (rect 161 59 227 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 64)(pt 232 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 80)
|
||||
(output)
|
||||
(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "COND" (rect 191 75 227 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 80)(pt 232 80))
|
||||
)
|
||||
(port
|
||||
(pt 248 96)
|
||||
(output)
|
||||
(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CARRY" (rect 186 91 227 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 96)(pt 232 96))
|
||||
)
|
||||
(port
|
||||
(pt 248 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 89 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "jumpflags[7..0]" (rect 138 107 227 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 112)(pt 232 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 128)
|
||||
(output)
|
||||
(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL_res[31..0]" (rect 137 75 227 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 80)(pt 232 80)(line_width 3))
|
||||
(text "MUL_res[31..0]" (rect 137 123 227 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 128)(pt 232 128)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 232 176))
|
||||
|
|
|
|||
852
CPUProject.bdf
852
CPUProject.bdf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(properties
|
||||
|
|
@ -742,6 +743,54 @@ refer to the applicable agreement for further details.
|
|||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 1512 352 1688 368)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "jumpflags[7..0]" (rect 90 0 164 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 1512 368 1688 384)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "mul1[15..0]" (rect 90 0 145 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 1512 384 1688 400)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "mul2[15..0]" (rect 90 0 145 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 632 144 816 352)
|
||||
(text "mux_8x16" (rect 5 0 55 12)(font "Arial" ))
|
||||
|
|
@ -976,97 +1025,6 @@ refer to the applicable agreement for further details.
|
|||
(rectangle (rect 16 16 168 192))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 936 160 1152 304)
|
||||
(text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10)))
|
||||
(text "RAMd" (rect 8 128 37 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 18 64 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 34 34 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 50 86 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 98 33 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 114 33 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 177 18 219 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 109 24 121 57)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 12 132 67)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 130 137 142)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
(line (pt 104 96)(pt 104 24))
|
||||
(line (pt 118 58)(pt 123 63))
|
||||
(line (pt 118 62)(pt 123 57))
|
||||
(line (pt 88 27)(pt 96 27))
|
||||
(line (pt 96 27)(pt 96 39))
|
||||
(line (pt 96 39)(pt 88 39))
|
||||
(line (pt 88 39)(pt 88 27))
|
||||
(line (pt 88 34)(pt 90 36))
|
||||
(line (pt 90 36)(pt 88 38))
|
||||
(line (pt 80 36)(pt 88 36))
|
||||
(line (pt 96 32)(pt 104 32)(line_width 3))
|
||||
(line (pt 88 43)(pt 96 43))
|
||||
(line (pt 96 43)(pt 96 55))
|
||||
(line (pt 96 55)(pt 88 55))
|
||||
(line (pt 88 55)(pt 88 43))
|
||||
(line (pt 88 50)(pt 90 52))
|
||||
(line (pt 90 52)(pt 88 54))
|
||||
(line (pt 80 52)(pt 88 52))
|
||||
(line (pt 96 48)(pt 104 48))
|
||||
(line (pt 88 59)(pt 96 59))
|
||||
(line (pt 96 59)(pt 96 71))
|
||||
(line (pt 96 71)(pt 88 71))
|
||||
(line (pt 88 71)(pt 88 59))
|
||||
(line (pt 88 66)(pt 90 68))
|
||||
(line (pt 90 68)(pt 88 70))
|
||||
(line (pt 80 68)(pt 88 68))
|
||||
(line (pt 96 64)(pt 104 64)(line_width 3))
|
||||
(line (pt 80 112)(pt 80 36))
|
||||
(line (pt 0 0)(pt 217 0))
|
||||
(line (pt 217 0)(pt 217 146))
|
||||
(line (pt 0 146)(pt 217 146))
|
||||
(line (pt 0 0)(pt 0 146))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 200 160 408 512)
|
||||
(text "reg_file" (rect 5 0 49 19)(font "Intel Clear" (font_size 8)))
|
||||
|
|
@ -1419,189 +1377,6 @@ refer to the applicable agreement for further details.
|
|||
)
|
||||
(annotation_block (parameter)(rect 1368 272 1400 288))
|
||||
)
|
||||
(symbol
|
||||
(rect 936 304 1184 496)
|
||||
(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "ALU" (rect 8 171 28 188)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "ALU_en" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "ALU_en" (rect 21 27 67 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "Rs1[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rs1[15..0]" (rect 21 43 82 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "Rs2[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rs2[15..0]" (rect 21 59 82 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "Rd[15..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "stack_data[15..0]" (rect 0 0 103 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "stack_data[15..0]" (rect 21 123 124 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 248 32)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rout[15..0]" (rect 161 27 227 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 32)(pt 232 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 48)
|
||||
(output)
|
||||
(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "COND" (rect 191 43 227 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 48)(pt 232 48))
|
||||
)
|
||||
(port
|
||||
(pt 248 64)
|
||||
(output)
|
||||
(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CARRY" (rect 186 59 227 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 64)(pt 232 64))
|
||||
)
|
||||
(port
|
||||
(pt 248 80)
|
||||
(output)
|
||||
(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL_res[31..0]" (rect 137 75 227 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 80)(pt 232 80)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 232 176))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 600 -8 816 136)
|
||||
(text "ram_instr" (rect 81 0 144 16)(font "Arial" (font_size 10)))
|
||||
(text "RAMi" (rect 8 128 33 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 18 64 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 34 34 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 50 86 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 98 33 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 114 33 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 177 18 219 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 109 24 121 57)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 12 132 67)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 130 137 142)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
(line (pt 104 96)(pt 104 24))
|
||||
(line (pt 118 58)(pt 123 63))
|
||||
(line (pt 118 62)(pt 123 57))
|
||||
(line (pt 88 27)(pt 96 27))
|
||||
(line (pt 96 27)(pt 96 39))
|
||||
(line (pt 96 39)(pt 88 39))
|
||||
(line (pt 88 39)(pt 88 27))
|
||||
(line (pt 88 34)(pt 90 36))
|
||||
(line (pt 90 36)(pt 88 38))
|
||||
(line (pt 80 36)(pt 88 36))
|
||||
(line (pt 96 32)(pt 104 32)(line_width 3))
|
||||
(line (pt 88 43)(pt 96 43))
|
||||
(line (pt 96 43)(pt 96 55))
|
||||
(line (pt 96 55)(pt 88 55))
|
||||
(line (pt 88 55)(pt 88 43))
|
||||
(line (pt 88 50)(pt 90 52))
|
||||
(line (pt 90 52)(pt 88 54))
|
||||
(line (pt 80 52)(pt 88 52))
|
||||
(line (pt 96 48)(pt 104 48))
|
||||
(line (pt 88 59)(pt 96 59))
|
||||
(line (pt 96 59)(pt 96 71))
|
||||
(line (pt 96 71)(pt 88 71))
|
||||
(line (pt 88 71)(pt 88 59))
|
||||
(line (pt 88 66)(pt 90 68))
|
||||
(line (pt 90 68)(pt 88 70))
|
||||
(line (pt 80 68)(pt 88 68))
|
||||
(line (pt 96 64)(pt 104 64)(line_width 3))
|
||||
(line (pt 80 112)(pt 80 36))
|
||||
(line (pt 0 0)(pt 217 0))
|
||||
(line (pt 217 0)(pt 217 146))
|
||||
(line (pt 0 146)(pt 217 146))
|
||||
(line (pt 0 0)(pt 0 146))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 1168 -136 1376 264)
|
||||
(text "DECODE" (rect 5 0 52 12)(font "Arial" ))
|
||||
|
|
@ -1792,6 +1567,301 @@ refer to the applicable agreement for further details.
|
|||
(rectangle (rect 16 16 192 384))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 936 320 1184 512)
|
||||
(text "ALU_top" (rect 5 0 56 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "ALU" (rect 8 171 28 188)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "ALU_en" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "ALU_en" (rect 21 27 67 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "Rs1[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rs1[15..0]" (rect 21 43 82 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "Rs2[15..0]" (rect 0 0 61 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rs2[15..0]" (rect 21 59 82 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "Rd[15..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rd[15..0]" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "op[5..0]" (rect 0 0 46 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "op[5..0]" (rect 21 91 67 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "EXEC2" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "EXEC2" (rect 21 107 59 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "stack_data[15..0]" (rect 0 0 103 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "stack_data[15..0]" (rect 21 123 124 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLK" (rect 21 139 44 158)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 248 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "mul1[15..0]" (rect 158 27 227 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 32)(pt 232 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 69 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "mul2[15..0]" (rect 158 43 227 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 48)(pt 232 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 66 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "Rout[15..0]" (rect 161 59 227 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 64)(pt 232 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 80)
|
||||
(output)
|
||||
(text "COND" (rect 0 0 36 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "COND" (rect 191 75 227 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 80)(pt 232 80))
|
||||
)
|
||||
(port
|
||||
(pt 248 96)
|
||||
(output)
|
||||
(text "CARRY" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CARRY" (rect 186 91 227 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 96)(pt 232 96))
|
||||
)
|
||||
(port
|
||||
(pt 248 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 89 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "jumpflags[7..0]" (rect 138 107 227 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 112)(pt 232 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 128)
|
||||
(output)
|
||||
(text "MUL_res[31..0]" (rect 0 0 90 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL_res[31..0]" (rect 137 123 227 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 248 128)(pt 232 128)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 232 176))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 936 160 1152 304)
|
||||
(text "ram_data" (rect 74 0 137 16)(font "Arial" (font_size 10)))
|
||||
(text "RAMd" (rect 8 128 37 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 16 64 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 32 34 46)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 48 86 62)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 96 33 110)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 112 33 126)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 169 16 211 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 106 29 118 62)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 15 132 70)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 127 137 139)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
(line (pt 104 96)(pt 104 24))
|
||||
(line (pt 118 58)(pt 123 63))
|
||||
(line (pt 118 62)(pt 123 57))
|
||||
(line (pt 88 27)(pt 96 27))
|
||||
(line (pt 96 27)(pt 96 39))
|
||||
(line (pt 96 39)(pt 88 39))
|
||||
(line (pt 88 39)(pt 88 27))
|
||||
(line (pt 88 34)(pt 90 36))
|
||||
(line (pt 90 36)(pt 88 38))
|
||||
(line (pt 80 36)(pt 88 36))
|
||||
(line (pt 96 32)(pt 104 32)(line_width 3))
|
||||
(line (pt 88 43)(pt 96 43))
|
||||
(line (pt 96 43)(pt 96 55))
|
||||
(line (pt 96 55)(pt 88 55))
|
||||
(line (pt 88 55)(pt 88 43))
|
||||
(line (pt 88 50)(pt 90 52))
|
||||
(line (pt 90 52)(pt 88 54))
|
||||
(line (pt 80 52)(pt 88 52))
|
||||
(line (pt 96 48)(pt 104 48))
|
||||
(line (pt 88 59)(pt 96 59))
|
||||
(line (pt 96 59)(pt 96 71))
|
||||
(line (pt 96 71)(pt 88 71))
|
||||
(line (pt 88 71)(pt 88 59))
|
||||
(line (pt 88 66)(pt 90 68))
|
||||
(line (pt 90 68)(pt 88 70))
|
||||
(line (pt 80 68)(pt 88 68))
|
||||
(line (pt 96 64)(pt 104 64)(line_width 3))
|
||||
(line (pt 80 112)(pt 80 36))
|
||||
(line (pt 0 0)(pt 217 0))
|
||||
(line (pt 217 0)(pt 217 146))
|
||||
(line (pt 0 146)(pt 217 146))
|
||||
(line (pt 0 0)(pt 0 146))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 600 -8 816 136)
|
||||
(text "ram_instr" (rect 74 0 137 16)(font "Arial" (font_size 10)))
|
||||
(text "RAMi" (rect 8 128 33 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 16 64 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 32 34 46)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 48 86 62)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 96 33 110)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 112 33 126)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 169 16 211 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 106 29 118 62)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 15 132 70)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 127 137 139)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
(line (pt 104 96)(pt 104 24))
|
||||
(line (pt 118 58)(pt 123 63))
|
||||
(line (pt 118 62)(pt 123 57))
|
||||
(line (pt 88 27)(pt 96 27))
|
||||
(line (pt 96 27)(pt 96 39))
|
||||
(line (pt 96 39)(pt 88 39))
|
||||
(line (pt 88 39)(pt 88 27))
|
||||
(line (pt 88 34)(pt 90 36))
|
||||
(line (pt 90 36)(pt 88 38))
|
||||
(line (pt 80 36)(pt 88 36))
|
||||
(line (pt 96 32)(pt 104 32)(line_width 3))
|
||||
(line (pt 88 43)(pt 96 43))
|
||||
(line (pt 96 43)(pt 96 55))
|
||||
(line (pt 96 55)(pt 88 55))
|
||||
(line (pt 88 55)(pt 88 43))
|
||||
(line (pt 88 50)(pt 90 52))
|
||||
(line (pt 90 52)(pt 88 54))
|
||||
(line (pt 80 52)(pt 88 52))
|
||||
(line (pt 96 48)(pt 104 48))
|
||||
(line (pt 88 59)(pt 96 59))
|
||||
(line (pt 96 59)(pt 96 71))
|
||||
(line (pt 96 71)(pt 88 71))
|
||||
(line (pt 88 71)(pt 88 59))
|
||||
(line (pt 88 66)(pt 90 68))
|
||||
(line (pt 90 68)(pt 88 70))
|
||||
(line (pt 80 68)(pt 88 68))
|
||||
(line (pt 96 64)(pt 104 64)(line_width 3))
|
||||
(line (pt 80 112)(pt 80 36))
|
||||
(line (pt 0 0)(pt 217 0))
|
||||
(line (pt 217 0)(pt 217 146))
|
||||
(line (pt 0 146)(pt 217 146))
|
||||
(line (pt 0 0)(pt 0 146))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 856 192)
|
||||
(pt 936 192)
|
||||
|
|
@ -1824,36 +1894,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 856 592)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 352)
|
||||
(pt 936 352)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 192)
|
||||
(pt 856 352)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 592)
|
||||
(pt 856 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 384)
|
||||
(pt 936 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "ALU_en" (rect 890 320 927 337)(font "Intel Clear" ))
|
||||
(pt 936 336)
|
||||
(pt 880 336)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC2" (rect 890 400 921 417)(font "Intel Clear" ))
|
||||
(pt 936 416)
|
||||
(pt 880 416)
|
||||
)
|
||||
(connector
|
||||
(text "R0_en" (rect 162 192 192 209)(font "Intel Clear" ))
|
||||
(pt 200 208)
|
||||
|
|
@ -2186,22 +2226,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 576 720)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs2[15..0]" (rect 824 352 871 369)(font "Intel Clear" ))
|
||||
(pt 936 368)
|
||||
(pt 824 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 816 384)
|
||||
(pt 824 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 824 384)
|
||||
(pt 824 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "s2[2..0]" (rect 602 368 636 385)(font "Intel Clear" ))
|
||||
(pt 632 384)
|
||||
|
|
@ -2327,11 +2351,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 1376 216)
|
||||
(pt 1424 216)
|
||||
)
|
||||
(connector
|
||||
(pt 856 176)
|
||||
(pt 856 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs1[15..0]" (rect 818 160 865 177)(font "Intel Clear" ))
|
||||
(pt 816 176)
|
||||
|
|
@ -2556,23 +2575,11 @@ refer to the applicable agreement for further details.
|
|||
(pt 1440 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "RAMd_out[15..0]" (rect 1442 280 1522 297)(font "Intel Clear" ))
|
||||
(pt 1512 296)
|
||||
(pt 1432 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1450 312 1479 329)(font "Intel Clear" ))
|
||||
(pt 1512 328)
|
||||
(pt 1440 328)
|
||||
)
|
||||
(connector
|
||||
(text "instr[14..9]" (rect 890 384 939 401)(font "Intel Clear" ))
|
||||
(pt 936 400)
|
||||
(pt 880 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs1[15..0]" (rect 850 624 897 641)(font "Intel Clear" ))
|
||||
(pt 840 640)
|
||||
|
|
@ -2631,17 +2638,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 1144 640)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "CLK" (rect 890 432 910 449)(font "Intel Clear" ))
|
||||
(pt 936 448)
|
||||
(pt 880 448)
|
||||
)
|
||||
(connector
|
||||
(text "stack_out[15..0]" (rect 872 416 947 433)(font "Intel Clear" ))
|
||||
(pt 936 432)
|
||||
(pt 872 432)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "s4" (rect 1296 373 1313 383)(font "Intel Clear" )(vertical))
|
||||
(pt 1312 360)
|
||||
|
|
@ -2657,28 +2653,6 @@ refer to the applicable agreement for further details.
|
|||
(pt 344 712)
|
||||
(pt 400 712)
|
||||
)
|
||||
(connector
|
||||
(text "ALU_out[15..0]" (rect 1186 320 1256 337)(font "Intel Clear" ))
|
||||
(pt 1184 336)
|
||||
(pt 1256 336)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1194 336 1223 353)(font "Intel Clear" ))
|
||||
(pt 1184 352)
|
||||
(pt 1232 352)
|
||||
)
|
||||
(connector
|
||||
(text "CARRY" (rect 1186 352 1221 369)(font "Intel Clear" ))
|
||||
(pt 1184 368)
|
||||
(pt 1232 368)
|
||||
)
|
||||
(connector
|
||||
(text "MUL_res[31..0]" (rect 1184 368 1255 385)(font "Intel Clear" ))
|
||||
(pt 1184 384)
|
||||
(pt 1232 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "MUL_res[31..0]" (rect 1450 328 1521 345)(font "Intel Clear" ))
|
||||
(pt 1512 344)
|
||||
|
|
@ -2741,6 +2715,138 @@ refer to the applicable agreement for further details.
|
|||
(pt 272 88)
|
||||
(pt 304 88)
|
||||
)
|
||||
(connector
|
||||
(text "RAMd_out[15..0]" (rect 1450 280 1530 297)(font "Intel Clear" ))
|
||||
(pt 1512 296)
|
||||
(pt 1440 296)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "jumpflags[7..0]" (rect 1448 344 1518 361)(font "Intel Clear" ))
|
||||
(pt 1512 360)
|
||||
(pt 1440 360)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 592)
|
||||
(pt 856 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 176)
|
||||
(pt 856 192)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 192)
|
||||
(pt 856 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "ALU_en" (rect 890 336 927 353)(font "Intel Clear" ))
|
||||
(pt 880 352)
|
||||
(pt 936 352)
|
||||
)
|
||||
(connector
|
||||
(pt 856 368)
|
||||
(pt 936 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "Rs2[15..0]" (rect 824 368 871 385)(font "Intel Clear" ))
|
||||
(pt 816 384)
|
||||
(pt 936 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 400)
|
||||
(pt 936 400)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "instr[14..9]" (rect 890 400 939 417)(font "Intel Clear" ))
|
||||
(pt 880 416)
|
||||
(pt 936 416)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "EXEC2" (rect 890 416 921 433)(font "Intel Clear" ))
|
||||
(pt 880 432)
|
||||
(pt 936 432)
|
||||
)
|
||||
(connector
|
||||
(text "stack_out[15..0]" (rect 880 432 955 449)(font "Intel Clear" ))
|
||||
(pt 880 448)
|
||||
(pt 936 448)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "CLK" (rect 890 448 910 465)(font "Intel Clear" ))
|
||||
(pt 880 464)
|
||||
(pt 936 464)
|
||||
)
|
||||
(connector
|
||||
(pt 1256 336)
|
||||
(pt 1248 336)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1248 336)
|
||||
(pt 1248 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "ALU_out[15..0]" (rect 1186 368 1256 385)(font "Intel Clear" ))
|
||||
(pt 1184 384)
|
||||
(pt 1248 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
|
||||
(pt 1184 400)
|
||||
(pt 1232 400)
|
||||
)
|
||||
(connector
|
||||
(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
|
||||
(pt 1184 416)
|
||||
(pt 1232 416)
|
||||
)
|
||||
(connector
|
||||
(text "jumpflags[7..0]" (rect 1184 416 1254 433)(font "Intel Clear" ))
|
||||
(pt 1184 432)
|
||||
(pt 1232 432)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "MUL_res[31..0]" (rect 1184 432 1255 449)(font "Intel Clear" ))
|
||||
(pt 1184 448)
|
||||
(pt 1232 448)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul1[15..0]" (rect 1192 336 1246 353)(font "Intel Clear" ))
|
||||
(pt 1184 352)
|
||||
(pt 1232 352)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul2[15..0]" (rect 1192 352 1246 369)(font "Intel Clear" ))
|
||||
(pt 1184 368)
|
||||
(pt 1232 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul1[15..0]" (rect 1448 360 1502 377)(font "Intel Clear" ))
|
||||
(pt 1512 376)
|
||||
(pt 1440 376)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul2[15..0]" (rect 1448 376 1502 393)(font "Intel Clear" ))
|
||||
(pt 1512 392)
|
||||
(pt 1440 392)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 856 192))
|
||||
(junction (pt 136 320))
|
||||
(junction (pt 136 352))
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
|
@ -62,7 +62,6 @@ set_global_assignment -name POWER_USE_PVA ON
|
|||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE LIFOstack.v
|
||||
set_global_assignment -name VERILOG_FILE alu.v
|
||||
set_global_assignment -name MIF_FILE LUTSquares.mif
|
||||
|
|
@ -83,4 +82,6 @@ set_global_assignment -name BDF_FILE ALU_top.bdf
|
|||
set_global_assignment -name VERILOG_FILE mux_8x16.v
|
||||
set_global_assignment -name VERILOG_FILE mux_3x16.v
|
||||
set_global_assignment -name VERILOG_FILE ADD_1.v
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
BIN
CPUProject.qws
BIN
CPUProject.qws
Binary file not shown.
41
LUT.bsf
41
LUT.bsf
|
|
@ -22,47 +22,47 @@ https://fpgasoftware.intel.com/eula.
|
|||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 256 120)
|
||||
(text "LUT" (rect 102 0 129 16)(font "Arial" (font_size 10)))
|
||||
(text "LUT" (rect 112 0 139 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 8 149 31)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 16 92 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 40 148 63)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 48 92 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 72 51 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 176 96))
|
||||
(text "clock" (rect 4 80 33 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 104 96))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[15..0]" (rect 158 8 251 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 192 32)(line_width 3))
|
||||
(text "q_a[15..0]" (rect 195 16 251 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 64)
|
||||
(output)
|
||||
(text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[15..0]" (rect 159 40 251 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 64)(pt 192 64)(line_width 3))
|
||||
(text "q_b[15..0]" (rect 195 48 251 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 64)(pt 168 64)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "256 Word(s)" (rect 127 -1 253 231)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 148 -22 243 169)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 40 99 239 219)(font "Arial" ))
|
||||
(text "256 Word(s)" (rect 134 -14 234 186)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 148 -29 226 142)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 40 106 174 226)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24))
|
||||
(line (pt 168 24)(pt 168 80))
|
||||
(line (pt 168 80)(pt 128 80))
|
||||
|
|
@ -84,23 +84,6 @@ https://fpgasoftware.intel.com/eula.
|
|||
(line (pt 104 68)(pt 112 68))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 3))
|
||||
(line (pt 104 36)(pt 104 97))
|
||||
(line (pt 176 36)(pt 176 97))
|
||||
(line (pt 184 27)(pt 192 27))
|
||||
(line (pt 192 27)(pt 192 39))
|
||||
(line (pt 192 39)(pt 184 39))
|
||||
(line (pt 184 39)(pt 184 27))
|
||||
(line (pt 184 34)(pt 186 36))
|
||||
(line (pt 186 36)(pt 184 38))
|
||||
(line (pt 176 36)(pt 184 36))
|
||||
(line (pt 168 32)(pt 184 32)(line_width 3))
|
||||
(line (pt 184 59)(pt 192 59))
|
||||
(line (pt 192 59)(pt 192 71))
|
||||
(line (pt 192 71)(pt 184 71))
|
||||
(line (pt 184 71)(pt 184 59))
|
||||
(line (pt 184 66)(pt 186 68))
|
||||
(line (pt 186 68)(pt 184 70))
|
||||
(line (pt 176 68)(pt 184 68))
|
||||
(line (pt 168 64)(pt 184 64)(line_width 3))
|
||||
(line (pt 0 0)(pt 257 0))
|
||||
(line (pt 257 0)(pt 257 122))
|
||||
(line (pt 0 122)(pt 257 122))
|
||||
|
|
|
|||
1
LUT.qip
1
LUT.qip
|
|
@ -3,3 +3,4 @@ set_global_assignment -name IP_TOOL_VERSION "19.1"
|
|||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LUT.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT_bb.v"]
|
||||
|
|
|
|||
162
LUT_bb.v
Normal file
162
LUT_bb.v
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
// megafunction wizard: %ROM: 2-PORT%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: LUT.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details, at
|
||||
//https://fpgasoftware.intel.com/eula.
|
||||
|
||||
module LUT (
|
||||
address_a,
|
||||
address_b,
|
||||
clock,
|
||||
q_a,
|
||||
q_b);
|
||||
|
||||
input [7:0] address_a;
|
||||
input [7:0] address_b;
|
||||
input clock;
|
||||
output [15:0] q_a;
|
||||
output [15:0] q_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING "LUTSquares.mif"
|
||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: INIT_FILE STRING "LUTSquares.mif"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
|
||||
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
|
||||
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
|
||||
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
|
||||
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
48
alu.bsf
48
alu.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,11 +16,12 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 224 192)
|
||||
(rect 16 16 232 192)
|
||||
(text "alu" (rect 5 0 15 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 160 20 172)(font "Arial" ))
|
||||
(port
|
||||
|
|
@ -80,41 +81,48 @@ refer to the applicable agreement for further details.
|
|||
(line (pt 0 144)(pt 16 144)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 32)
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" ))
|
||||
(text "mul1[15..0]" (rect 146 27 187 39)(font "Arial" ))
|
||||
(line (pt 208 32)(pt 192 32)(line_width 3))
|
||||
(text "mul1[15..0]" (rect 154 27 195 39)(font "Arial" ))
|
||||
(line (pt 216 32)(pt 200 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 48)
|
||||
(pt 216 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" ))
|
||||
(text "mul2[15..0]" (rect 145 43 187 55)(font "Arial" ))
|
||||
(line (pt 208 48)(pt 192 48)(line_width 3))
|
||||
(text "mul2[15..0]" (rect 153 43 195 55)(font "Arial" ))
|
||||
(line (pt 216 48)(pt 200 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 64)
|
||||
(pt 216 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "Rout[15..0]" (rect 144 59 187 71)(font "Arial" ))
|
||||
(line (pt 208 64)(pt 192 64)(line_width 3))
|
||||
(text "Rout[15..0]" (rect 152 59 195 71)(font "Arial" ))
|
||||
(line (pt 216 64)(pt 200 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 80)
|
||||
(pt 216 80)
|
||||
(output)
|
||||
(text "jump" (rect 0 0 18 12)(font "Arial" ))
|
||||
(text "jump" (rect 169 75 187 87)(font "Arial" ))
|
||||
(line (pt 208 80)(pt 192 80)(line_width 1))
|
||||
(text "jump" (rect 177 75 195 87)(font "Arial" ))
|
||||
(line (pt 216 80)(pt 200 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 208 96)
|
||||
(pt 216 96)
|
||||
(output)
|
||||
(text "carry" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "carry" (rect 165 91 187 103)(font "Arial" ))
|
||||
(line (pt 208 96)(pt 192 96)(line_width 1))
|
||||
(text "carry" (rect 173 91 195 103)(font "Arial" ))
|
||||
(line (pt 216 96)(pt 200 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
|
||||
(text "jumpflags[7..0]" (rect 138 107 195 119)(font "Arial" ))
|
||||
(line (pt 216 112)(pt 200 112)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 192 160)(line_width 1))
|
||||
(rectangle (rect 16 16 200 160)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
|
|||
29
data.mif
29
data.mif
|
|
@ -1,6 +1,6 @@
|
|||
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
|
|
@ -10,7 +10,8 @@
|
|||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
-- Quartus Prime generated Memory Initialization File (.mif)
|
||||
|
||||
|
|
@ -27,18 +28,16 @@ CONTENT BEGIN
|
|||
003 : FFFF;
|
||||
004 : BFFF;
|
||||
005 : 000A;
|
||||
006 : 0017;
|
||||
007 : 001A;
|
||||
008 : 001D;
|
||||
009 : 0020;
|
||||
00A : 0024;
|
||||
006 : 001B;
|
||||
007 : 001E;
|
||||
008 : 0021;
|
||||
009 : 0024;
|
||||
00A : 0028;
|
||||
00B : 0000;
|
||||
00C : 0027;
|
||||
00D : 002A;
|
||||
00E : 002D;
|
||||
00F : 0032;
|
||||
00C : 002B;
|
||||
00D : 002E;
|
||||
00E : 0031;
|
||||
00F : 0036;
|
||||
010 : AAAA;
|
||||
011 : 0004;
|
||||
012 : FFF0;
|
||||
[013..7FF] : 0000;
|
||||
[011..7FF] : 0000;
|
||||
END;
|
||||
|
|
|
|||
119
instr.mif
119
instr.mif
|
|
@ -1,6 +1,6 @@
|
|||
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
|
|
@ -10,7 +10,8 @@
|
|||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details.
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
-- Quartus Prime generated Memory Initialization File (.mif)
|
||||
|
||||
|
|
@ -28,58 +29,62 @@ CONTENT BEGIN
|
|||
4 : 2D20;
|
||||
5 : 3161;
|
||||
6 : 3448;
|
||||
7 : D002;
|
||||
8 : B002;
|
||||
9 : 9804;
|
||||
10 : B811;
|
||||
11 : 419F;
|
||||
12 : 304F;
|
||||
13 : 5008;
|
||||
14 : 5028;
|
||||
15 : 284F;
|
||||
16 : 43F7;
|
||||
17 : 3568;
|
||||
18 : 45F5;
|
||||
19 : 484D;
|
||||
20 : 8806;
|
||||
21 : 0040;
|
||||
22 : B800;
|
||||
23 : 8807;
|
||||
24 : 085A;
|
||||
25 : B800;
|
||||
26 : 8808;
|
||||
27 : 0A6F;
|
||||
28 : B800;
|
||||
29 : 8809;
|
||||
30 : 0C53;
|
||||
31 : B801;
|
||||
32 : 880A;
|
||||
33 : B00B;
|
||||
34 : 0E70;
|
||||
35 : B800;
|
||||
36 : 880C;
|
||||
37 : 1063;
|
||||
38 : B800;
|
||||
39 : 880D;
|
||||
40 : 126D;
|
||||
41 : B800;
|
||||
42 : 880E;
|
||||
43 : 147E;
|
||||
44 : B800;
|
||||
45 : 880F;
|
||||
46 : 5340;
|
||||
47 : 53C0;
|
||||
48 : 1678;
|
||||
49 : B800;
|
||||
50 : 1863;
|
||||
51 : 1A5F;
|
||||
52 : 1FB8;
|
||||
53 : 7C00;
|
||||
54 : 1C77;
|
||||
55 : 204C;
|
||||
56 : A810;
|
||||
57 : 226D;
|
||||
58 : 246D;
|
||||
59 : 7E00;
|
||||
[60..2047] : 0000;
|
||||
7 : 3993;
|
||||
8 : 3AA5;
|
||||
9 : D002;
|
||||
10 : 3CE2;
|
||||
11 : A003;
|
||||
12 : 9804;
|
||||
13 : 38A5;
|
||||
14 : 3FC0;
|
||||
15 : 419D;
|
||||
16 : 304F;
|
||||
17 : 5008;
|
||||
18 : 5028;
|
||||
19 : 284F;
|
||||
20 : 43F1;
|
||||
21 : 3568;
|
||||
22 : 45F5;
|
||||
23 : 484D;
|
||||
24 : 8806;
|
||||
25 : 0040;
|
||||
26 : B800;
|
||||
27 : 8807;
|
||||
28 : 085A;
|
||||
29 : B800;
|
||||
30 : 8808;
|
||||
31 : 0A6F;
|
||||
32 : B800;
|
||||
33 : 8809;
|
||||
34 : 0C53;
|
||||
35 : B801;
|
||||
36 : 880A;
|
||||
37 : B00B;
|
||||
38 : 0E70;
|
||||
39 : B800;
|
||||
40 : 880C;
|
||||
41 : 1063;
|
||||
42 : B800;
|
||||
43 : 880D;
|
||||
44 : 126D;
|
||||
45 : B800;
|
||||
46 : 880E;
|
||||
47 : 147A;
|
||||
48 : B800;
|
||||
49 : 880F;
|
||||
50 : 5340;
|
||||
51 : 53C0;
|
||||
52 : 1660;
|
||||
53 : B801;
|
||||
54 : 1863;
|
||||
55 : 1A5A;
|
||||
56 : 1FB8;
|
||||
57 : 7C00;
|
||||
58 : 1C6F;
|
||||
59 : 204C;
|
||||
60 : A810;
|
||||
61 : 226D;
|
||||
62 : 246D;
|
||||
63 : 7E00;
|
||||
[64..2047] : 0000;
|
||||
END;
|
||||
|
|
|
|||
286
mul16.bdf
286
mul16.bdf
|
|
@ -22,55 +22,55 @@ https://fpgasoftware.intel.com/eula.
|
|||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 48 256 216 272)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "A[15..0]" (rect 5 0 43 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(rect 48 256 224 272)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "A[15..0]" (rect 9 0 47 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 304 208 320)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "B[15..0]" (rect 5 0 43 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(rect 40 304 216 320)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "B[15..0]" (rect 9 0 47 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 40 208 208 224)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "CLOCK" (rect 5 0 42 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(rect 40 208 216 224)
|
||||
(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
|
||||
(text "CLOCK" (rect 9 0 46 12)(font "Arial" ))
|
||||
(pt 176 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
(line (pt 92 12)(pt 117 12))
|
||||
(line (pt 92 4)(pt 117 4))
|
||||
(line (pt 121 8)(pt 176 8))
|
||||
(line (pt 92 12)(pt 92 4))
|
||||
(line (pt 117 4)(pt 121 8))
|
||||
(line (pt 117 12)(pt 121 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 1872 272 2054 288)
|
||||
(rect 1872 272 2048 288)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "PRODUCT[31..0]" (rect 90 0 176 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
|
|
@ -89,12 +89,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
|
||||
(text "ADD2" (rect 3 156 32 168)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 144)
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
|
|
@ -103,6 +102,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 15 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
|
|
@ -112,11 +118,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
|
|
@ -128,24 +134,18 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 160 144)
|
||||
(output)
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 144)(pt 160 144))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -153,7 +153,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 128)
|
||||
(output)
|
||||
(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 128)(pt 160 128))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -161,15 +161,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 96)
|
||||
(output)
|
||||
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 96)(pt 160 96)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"LPM_DIRECTION"
|
||||
"\"ADD\""
|
||||
"ADD"
|
||||
"Selects between addition, subtraction, or both"
|
||||
"\"DEFAULT\"" "\"ADD\"" "\"SUB\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_PIPELINE"
|
||||
""
|
||||
|
|
@ -178,10 +178,10 @@ https://fpgasoftware.intel.com/eula.
|
|||
)
|
||||
(parameter
|
||||
"LPM_REPRESENTATION"
|
||||
"\"UNSIGNED\""
|
||||
"UNSIGNED"
|
||||
"Numeric representation of inputs"
|
||||
"\"UNSIGNED\"" "\"SIGNED\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_WIDTH"
|
||||
"32"
|
||||
|
|
@ -228,14 +228,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
(symbol
|
||||
(rect 1264 48 1424 216)
|
||||
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
|
||||
(text "ADD3" (rect 3 156 30 173)(font "Intel Clear" ))
|
||||
(text "ADD3" (rect 3 156 32 168)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 144)
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
|
|
@ -244,6 +243,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 15 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
|
|
@ -253,11 +259,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
|
|
@ -269,24 +275,18 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 160 144)
|
||||
(output)
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 144)(pt 160 144))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -294,7 +294,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 128)
|
||||
(output)
|
||||
(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 128)(pt 160 128))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -302,15 +302,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 96)
|
||||
(output)
|
||||
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 96)(pt 160 96)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"LPM_DIRECTION"
|
||||
"\"ADD\""
|
||||
"ADD"
|
||||
"Selects between addition, subtraction, or both"
|
||||
"\"DEFAULT\"" "\"ADD\"" "\"SUB\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_PIPELINE"
|
||||
""
|
||||
|
|
@ -319,10 +319,10 @@ https://fpgasoftware.intel.com/eula.
|
|||
)
|
||||
(parameter
|
||||
"LPM_REPRESENTATION"
|
||||
"\"UNSIGNED\""
|
||||
"UNSIGNED"
|
||||
"Numeric representation of inputs"
|
||||
"\"UNSIGNED\"" "\"SIGNED\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_WIDTH"
|
||||
"32"
|
||||
|
|
@ -369,14 +369,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
(symbol
|
||||
(rect 1568 184 1728 352)
|
||||
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
|
||||
(text "ADD4" (rect 3 156 30 173)(font "Intel Clear" ))
|
||||
(text "ADD4" (rect 3 156 32 168)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 144)
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
|
|
@ -385,6 +384,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 15 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
|
|
@ -394,11 +400,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
|
|
@ -410,24 +416,18 @@ https://fpgasoftware.intel.com/eula.
|
|||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 160 144)
|
||||
(output)
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 140 143)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 144)(pt 160 144))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -435,7 +435,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 128)
|
||||
(output)
|
||||
(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 140 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 128)(pt 160 128))
|
||||
(unused)
|
||||
)
|
||||
|
|
@ -443,15 +443,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 160 96)
|
||||
(output)
|
||||
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 140 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 96)(pt 160 96)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"LPM_DIRECTION"
|
||||
"\"ADD\""
|
||||
"ADD"
|
||||
"Selects between addition, subtraction, or both"
|
||||
"\"DEFAULT\"" "\"ADD\"" "\"SUB\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_PIPELINE"
|
||||
""
|
||||
|
|
@ -460,10 +460,10 @@ https://fpgasoftware.intel.com/eula.
|
|||
)
|
||||
(parameter
|
||||
"LPM_REPRESENTATION"
|
||||
"\"UNSIGNED\""
|
||||
"UNSIGNED"
|
||||
"Numeric representation of inputs"
|
||||
"\"UNSIGNED\"" "\"SIGNED\""
|
||||
(type "PARAMETER_UNKNOWN") )
|
||||
(type "PARAMETER_STRING") )
|
||||
(parameter
|
||||
"LPM_WIDTH"
|
||||
"32"
|
||||
|
|
@ -654,7 +654,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
(symbol
|
||||
(rect 168 160 200 192)
|
||||
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
|
||||
(text "inst5" (rect 3 21 25 38)(font "Intel Clear" )(invisible))
|
||||
(text "inst5" (rect 3 21 26 33)(font "Arial" )(invisible))
|
||||
(port
|
||||
(pt 16 0)
|
||||
(output)
|
||||
|
|
@ -668,16 +668,6 @@ https://fpgasoftware.intel.com/eula.
|
|||
(line (pt 8 8)(pt 24 8))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 208 312)
|
||||
(pt 376 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 264)
|
||||
(pt 376 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "B[15..8]" (rect 570 104 606 121)(font "Intel Clear" ))
|
||||
(pt 648 120)
|
||||
|
|
@ -750,14 +740,6 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 888 424)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 200 216)
|
||||
(pt 208 216)
|
||||
)
|
||||
(connector
|
||||
(pt 208 216)
|
||||
(pt 520 216)
|
||||
)
|
||||
(connector
|
||||
(pt 520 88)
|
||||
(pt 648 88)
|
||||
|
|
@ -855,7 +837,37 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 1872 280)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 208 216))
|
||||
(connector
|
||||
(pt 208 312)
|
||||
(pt 216 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 312)
|
||||
(pt 376 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 216 264)
|
||||
(pt 224 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 224 264)
|
||||
(pt 376 264)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 200 216)
|
||||
(pt 216 216)
|
||||
)
|
||||
(connector
|
||||
(pt 216 216)
|
||||
(pt 520 216)
|
||||
)
|
||||
(junction (pt 520 208))
|
||||
(junction (pt 520 216))
|
||||
(junction (pt 520 320))
|
||||
(junction (pt 216 312))
|
||||
(junction (pt 224 264))
|
||||
(junction (pt 216 216))
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,7 +16,8 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
|
|
|
|||
167
mul8.bdf
167
mul8.bdf
|
|
@ -56,7 +56,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
(input)
|
||||
(rect 320 40 488 56)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "CLOCK" (rect 5 0 43 12)(font "Arial" ))
|
||||
(text "CLOCK" (rect 5 0 42 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
|
|
@ -664,97 +664,6 @@ https://fpgasoftware.intel.com/eula.
|
|||
(rectangle (rect 16 16 136 80))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 688 -48 944 72)
|
||||
(text "LUT" (rect 102 0 129 16)(font "Arial" (font_size 10)))
|
||||
(text "LookupTable" (rect 8 104 70 121)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 8 93 22)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 40 93 54)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 72 33 86)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 176 96))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[15..0]" (rect 158 8 214 22)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 64)
|
||||
(output)
|
||||
(text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[15..0]" (rect 159 40 215 54)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 64)(pt 192 64)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "256 Word(s)" (rect 127 -1 139 59)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 148 -22 160 1)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 40 99 132 111)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24))
|
||||
(line (pt 168 24)(pt 168 80))
|
||||
(line (pt 168 80)(pt 128 80))
|
||||
(line (pt 128 80)(pt 128 24))
|
||||
(line (pt 112 27)(pt 120 27))
|
||||
(line (pt 120 27)(pt 120 39))
|
||||
(line (pt 120 39)(pt 112 39))
|
||||
(line (pt 112 39)(pt 112 27))
|
||||
(line (pt 112 34)(pt 114 36))
|
||||
(line (pt 114 36)(pt 112 38))
|
||||
(line (pt 104 36)(pt 112 36))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59))
|
||||
(line (pt 120 59)(pt 120 71))
|
||||
(line (pt 120 71)(pt 112 71))
|
||||
(line (pt 112 71)(pt 112 59))
|
||||
(line (pt 112 66)(pt 114 68))
|
||||
(line (pt 114 68)(pt 112 70))
|
||||
(line (pt 104 68)(pt 112 68))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 3))
|
||||
(line (pt 104 36)(pt 104 97))
|
||||
(line (pt 176 36)(pt 176 97))
|
||||
(line (pt 184 27)(pt 192 27))
|
||||
(line (pt 192 27)(pt 192 39))
|
||||
(line (pt 192 39)(pt 184 39))
|
||||
(line (pt 184 39)(pt 184 27))
|
||||
(line (pt 184 34)(pt 186 36))
|
||||
(line (pt 186 36)(pt 184 38))
|
||||
(line (pt 176 36)(pt 184 36))
|
||||
(line (pt 168 32)(pt 184 32)(line_width 3))
|
||||
(line (pt 184 59)(pt 192 59))
|
||||
(line (pt 192 59)(pt 192 71))
|
||||
(line (pt 192 71)(pt 184 71))
|
||||
(line (pt 184 71)(pt 184 59))
|
||||
(line (pt 184 66)(pt 186 68))
|
||||
(line (pt 186 68)(pt 184 70))
|
||||
(line (pt 176 68)(pt 184 68))
|
||||
(line (pt 168 64)(pt 184 64)(line_width 3))
|
||||
(line (pt 0 0)(pt 257 0))
|
||||
(line (pt 257 0)(pt 257 122))
|
||||
(line (pt 0 122)(pt 257 122))
|
||||
(line (pt 0 0)(pt 0 122))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 360 440 520 552)
|
||||
(text "min" (rect 5 0 22 12)(font "Arial" ))
|
||||
|
|
@ -791,6 +700,80 @@ https://fpgasoftware.intel.com/eula.
|
|||
(rectangle (rect 16 16 144 96))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 688 -48 944 72)
|
||||
(text "LUT" (rect 112 0 139 16)(font "Arial" (font_size 10)))
|
||||
(text "LookupTable" (rect 8 104 69 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 16 93 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 48 93 62)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 80 33 94)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 104 96))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[15..0]" (rect 195 16 251 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 64)
|
||||
(output)
|
||||
(text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[15..0]" (rect 195 48 251 62)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 64)(pt 168 64)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "256 Word(s)" (rect 134 -14 146 46)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 148 -29 160 -6)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 40 106 132 118)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24))
|
||||
(line (pt 168 24)(pt 168 80))
|
||||
(line (pt 168 80)(pt 128 80))
|
||||
(line (pt 128 80)(pt 128 24))
|
||||
(line (pt 112 27)(pt 120 27))
|
||||
(line (pt 120 27)(pt 120 39))
|
||||
(line (pt 120 39)(pt 112 39))
|
||||
(line (pt 112 39)(pt 112 27))
|
||||
(line (pt 112 34)(pt 114 36))
|
||||
(line (pt 114 36)(pt 112 38))
|
||||
(line (pt 104 36)(pt 112 36))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59))
|
||||
(line (pt 120 59)(pt 120 71))
|
||||
(line (pt 120 71)(pt 112 71))
|
||||
(line (pt 112 71)(pt 112 59))
|
||||
(line (pt 112 66)(pt 114 68))
|
||||
(line (pt 114 68)(pt 112 70))
|
||||
(line (pt 104 68)(pt 112 68))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 3))
|
||||
(line (pt 104 36)(pt 104 97))
|
||||
(line (pt 0 0)(pt 257 0))
|
||||
(line (pt 257 0)(pt 257 122))
|
||||
(line (pt 0 122)(pt 257 122))
|
||||
(line (pt 0 0)(pt 0 122))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(text "1" (rect -94 -64 -89 -47)(font "Intel Clear" ))
|
||||
(pt -80 -48)
|
||||
|
|
|
|||
27
ram_data.bsf
27
ram_data.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,59 +16,60 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 216 144)
|
||||
(text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10)))
|
||||
(text "ram_data" (rect 74 0 137 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 128 25 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 18 53 31)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 16 64 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 32 29 47)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 50 72 63)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 48 85 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 96 33 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 112 33 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 177 18 211 31)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 169 16 211 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" ))
|
||||
(text "16 bits" (rect 106 29 198 170)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 15 226 198)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 127 186 268)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "19.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_data.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_data.bsf"]
|
||||
|
|
|
|||
|
|
@ -14,13 +14,13 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
|
|
@ -30,7 +30,8 @@
|
|||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
//refer to the applicable agreement for further details, at
|
||||
//https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,59 +16,60 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 216 144)
|
||||
(text "ram_instr" (rect 81 0 144 16)(font "Arial" (font_size 10)))
|
||||
(text "ram_instr" (rect 74 0 137 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 128 25 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 18 53 31)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 16 64 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 88 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 32 29 47)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 88 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 50 72 63)(font "Arial" (font_size 8)))
|
||||
(text "address[10..0]" (rect 4 48 85 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 88 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 4 96 33 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 80 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 114 27 127)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 4 112 33 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(output)
|
||||
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 177 18 211 31)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 169 16 211 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 bits" (rect 109 24 194 159)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 130 170 271)(font "Arial" ))
|
||||
(text "16 bits" (rect 106 29 198 170)(font "Arial" )(vertical))
|
||||
(text "2048 words" (rect 120 15 226 198)(font "Arial" )(vertical))
|
||||
(text "Block type: AUTO" (rect 48 127 186 268)(font "Arial" ))
|
||||
(line (pt 104 24)(pt 136 24))
|
||||
(line (pt 136 24)(pt 136 96))
|
||||
(line (pt 136 96)(pt 104 96))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "19.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"]
|
||||
|
|
|
|||
|
|
@ -14,13 +14,13 @@
|
|||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
|
|
@ -30,7 +30,8 @@
|
|||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
//refer to the applicable agreement for further details, at
|
||||
//https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
|
|
|
|||
Loading…
Reference in a new issue