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Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog
55 commits 1 branch 0 tags 69 MiB
Verilog 81.9%
C++ 17.8%
Tcl 0.3%
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Aadi Desai 4688a56452 Modified Test Program to add LDR and STR 
Also fixed logic within decoder for LDR and STR
2020-06-10 15:51:51 +01:00
.gitignore Added new test mif with no multiplication 2020-06-08 13:13:26 +01:00
abs.bdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
abs.bsf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
ADD_1.bsf Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
ADD_1.v Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
ADD_1.v.bak Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
all_instr_test.mif Fixed instrGen and added large test 2020-06-07 17:41:37 +01:00
all_instr_test.txt Fixed instrGen and added large test 2020-06-07 17:41:37 +01:00
alu.bsf Added LDR and STR to alu and set up data paths 2020-06-10 14:02:15 +01:00
alu.v Added LDR and STR to alu and set up data paths 2020-06-10 14:02:15 +01:00
alu.v.bak ALU now uses multiply block rather than * operator 2020-06-03 15:15:44 +01:00
ALU_top.bdf Added LDR and STR to alu and set up data paths 2020-06-10 14:02:15 +01:00
ALU_top.bsf Added LDR and STR to alu and set up data paths 2020-06-10 14:02:15 +01:00
CPUProject.bdf Modified Test Program to add LDR and STR 2020-06-10 15:51:51 +01:00
CPUProject.qpf Basic Project Setup 2020-05-20 12:44:57 +01:00
CPUProject.qsf Modified Test Program to add LDR and STR 2020-06-10 15:51:51 +01:00
CPUProject_assignment_defaults.qdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
data.mif Final State before Pipelining 2020-06-09 22:45:20 +01:00
DECODE.bsf Modified Test Program to add LDR and STR 2020-06-10 15:51:51 +01:00
DECODE.v Modified Test Program to add LDR and STR 2020-06-10 15:51:51 +01:00
DECODE.v.bak Fixed decoder and SM 2020-06-02 20:09:22 +01:00
Initial MUX 8x16 design.PNG Almost ready CPU 2020-06-07 15:08:34 +01:00
instr.mif Modified Test Program to add LDR and STR 2020-06-10 15:51:51 +01:00
InstructionGenerator.cpp Added STR and LDR to the cpp generator 2020-06-10 13:00:40 +01:00
LIFOstack.bsf Almost ready CPU 2020-06-07 15:08:34 +01:00
LIFOstack.v Update LIFOstack to support 32 memory slots 2020-06-07 20:05:46 +01:00
LIFOstack.v.bak Almost ready CPU 2020-06-07 15:08:34 +01:00
LUT.bsf Final State before Pipelining 2020-06-09 22:45:20 +01:00
LUT.qip Final State before Pipelining 2020-06-09 22:45:20 +01:00
LUT.v Updated LUT to have an unregistered output 2020-06-09 20:33:10 +01:00
LUT_bb.v Final State before Pipelining 2020-06-09 22:45:20 +01:00
LUTSquares.mif Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
min.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v.bak Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul8.bdf Final State before Pipelining 2020-06-09 22:45:20 +01:00
mul8.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul16.bdf Final State before Pipelining 2020-06-09 22:45:20 +01:00
mul16.bsf Final State before Pipelining 2020-06-09 22:45:20 +01:00
mux_3x16.bsf Almost ready CPU 2020-06-07 15:08:34 +01:00
mux_3x16.v Recompiled certain files 2020-06-08 12:10:14 +01:00
mux_3x16.v.bak Recompiled certain files 2020-06-08 12:10:14 +01:00
mux_8x16.bsf Almost ready CPU 2020-06-07 15:08:34 +01:00
mux_8x16.v Recompiled certain files 2020-06-08 12:10:14 +01:00
mux_8x16.v.bak Almost ready CPU 2020-06-07 15:08:34 +01:00
ram_data.bsf Final State before Pipelining 2020-06-09 22:45:20 +01:00
ram_data.qip Final State before Pipelining 2020-06-09 22:45:20 +01:00
ram_data.v Final State before Pipelining 2020-06-09 22:45:20 +01:00
ram_instr.bsf Final State before Pipelining 2020-06-09 22:45:20 +01:00
ram_instr.qip Final State before Pipelining 2020-06-09 22:45:20 +01:00
ram_instr.v Final State before Pipelining 2020-06-09 22:45:20 +01:00
README.md Initial commit 2020-05-20 12:05:19 +01:00
reg_file.bdf Debugging CPU 2020-06-07 20:51:33 +01:00
reg_file.bsf Working on initial design 2020-05-25 17:16:24 +01:00
SM.bsf Debugging CPU 2020-06-07 20:51:33 +01:00
SM.v Debugging complete! 2020-06-08 23:07:52 +01:00
SM.v.bak Fixed decoder and SM 2020-06-02 20:09:22 +01:00
SM_pipelined.v Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
SM_pipelined.v.bak Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
SquareMIFGenerator.cpp Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
test_no_mul.mif Added new test mif with no multiplication 2020-06-08 13:13:26 +01:00
test_no_mul.txt Update test_no_mul.txt 2020-06-09 12:11:06 +01:00

README.md

CPUProject