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https://github.com/supleed2/ELEC40006-P1-CW.git
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Added pipelined SM and block needed for pipelining
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778dd7f538
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50
ADD_1.bsf
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50
ADD_1.bsf
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 184 96)
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(text "ADD_1" (rect 5 0 36 12)(font "Arial" ))
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(text "inst" (rect 8 64 20 76)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "enable" (rect 0 0 24 12)(font "Arial" ))
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(text "enable" (rect 21 27 45 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "in[15..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "in[15..0]" (rect 21 43 50 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 168 32)
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(output)
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(text "out[15..0]" (rect 0 0 35 12)(font "Arial" ))
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(text "out[15..0]" (rect 112 27 147 39)(font "Arial" ))
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(line (pt 168 32)(pt 152 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 152 64)(line_width 1))
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)
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)
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ADD_1.v
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ADD_1.v
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module ADD_1 (enable, in, out);
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input [15:0] in;
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input enable;
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output reg [15:0] out;
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always @(*) begin
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if(enable)
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out = in + 1'b1;
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else
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out = in;
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end
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endmodule
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14
ADD_1.v.bak
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ADD_1.v.bak
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module ADD_1 (enable, in, out);
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input [15..0] in;
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input enable;
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output reg [15..0] out;
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always @(*) begin
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if(enable)
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out = in + 1'b1;
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else
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out = in;
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end
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endmodule
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@ -38,17 +38,13 @@
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
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set_global_assignment -name TOP_LEVEL_ENTITY SM_pipelined
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VERILOG_FILE LIFOstack.v
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set_global_assignment -name VERILOG_FILE alu.v
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set_global_assignment -name MIF_FILE LUTSquares.mif
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@ -67,4 +63,28 @@ set_global_assignment -name VERILOG_FILE min.v
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set_global_assignment -name VERILOG_FILE SM.v
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set_global_assignment -name BDF_FILE ALU_top.bdf
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set_global_assignment -name VERILOG_FILE mux_8x16.v
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set_global_assignment -name VERILOG_FILE mux_3x16.v
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set_global_assignment -name VERILOG_FILE mux_3x16.v
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set_global_assignment -name VERILOG_FILE ADD_1.v
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
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set_global_assignment -name POWER_USE_INPUT_FILES ON
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
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set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
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set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME ADD_1 -section_id eda_simulation
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_global_assignment -name POWER_USE_PVA ON
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set_global_assignment -name VERILOG_FILE SM_pipelined.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name POWER_INPUT_FILE_NAME simulation/qsim/CPUProject.msim.vcd -section_id cpuproject.msim.vcd
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set_instance_assignment -name POWER_READ_INPUT_FILE cpuproject.msim.vcd -to ADD_1
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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BIN
CPUProject.qws
BIN
CPUProject.qws
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SM_pipelined.v
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SM_pipelined.v
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module SM_pipelined (CLK, RST, E2, EXEC1, EXEC2);
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input CLK;
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input RST;
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input E2;
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output EXEC1;
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output EXEC2;
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reg s = 0;
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assign EXEC1 = ~s;
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assign EXEC2 = s;
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always @(posedge CLK) begin
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if(!RST)
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if(!s)
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if(E2)
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s <= 1;
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else
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s <= 0;
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else
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s <= 0;
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else
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s <= 0;
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end
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endmodule
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SM_pipelined.v.bak
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SM_pipelined.v.bak
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module SM_piplined (CLK, RST, E2, EXEC1, EXEC2);
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input CLK;
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input RST;
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input E2;
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output EXEC1;
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output EXEC2;
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reg s;
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always @(posedge CLK) begin
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if(!RST)
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if(!s)
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if(E2)
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s = 1'b1;
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else ;
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else
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s = 1'b0;
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else
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s = 1'b0;
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end
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assign EXEC1 = ~s;
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assign EXEC2 = s;
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endmodule
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