diff --git a/ADD_1.bsf b/ADD_1.bsf
new file mode 100644
index 0000000..f00e722
--- /dev/null
+++ b/ADD_1.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 184 96)
+	(text "ADD_1" (rect 5 0 36 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "enable" (rect 0 0 24 12)(font "Arial" ))
+		(text "enable" (rect 21 27 45 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "in[15..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "in[15..0]" (rect 21 43 50 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "out[15..0]" (rect 0 0 35 12)(font "Arial" ))
+		(text "out[15..0]" (rect 112 27 147 39)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 152 64)(line_width 1))
+	)
+)
diff --git a/ADD_1.v b/ADD_1.v
new file mode 100644
index 0000000..f89b481
--- /dev/null
+++ b/ADD_1.v
@@ -0,0 +1,14 @@
+module ADD_1 (enable, in, out);
+
+input [15:0] in;
+input enable;
+output reg [15:0] out;
+
+always @(*) begin
+	if(enable)
+		out = in + 1'b1;
+	else
+		out = in;
+end
+
+endmodule
\ No newline at end of file
diff --git a/ADD_1.v.bak b/ADD_1.v.bak
new file mode 100644
index 0000000..ac563df
--- /dev/null
+++ b/ADD_1.v.bak
@@ -0,0 +1,14 @@
+module ADD_1 (enable, in, out);
+
+input [15..0] in;
+input enable;
+output reg [15..0] out;
+
+always @(*) begin
+	if(enable)
+		out = in + 1'b1;
+	else
+		out = in;
+end
+
+endmodule
\ No newline at end of file
diff --git a/CPUProject.qsf b/CPUProject.qsf
index 28084ff..82edde9 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -38,17 +38,13 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
+set_global_assignment -name TOP_LEVEL_ENTITY SM_pipelined
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
 set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name VERILOG_FILE LIFOstack.v
 set_global_assignment -name VERILOG_FILE alu.v
 set_global_assignment -name MIF_FILE LUTSquares.mif
@@ -67,4 +63,28 @@ set_global_assignment -name VERILOG_FILE min.v
 set_global_assignment -name VERILOG_FILE SM.v
 set_global_assignment -name BDF_FILE ALU_top.bdf
 set_global_assignment -name VERILOG_FILE mux_8x16.v
-set_global_assignment -name VERILOG_FILE mux_3x16.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE mux_3x16.v
+set_global_assignment -name VERILOG_FILE ADD_1.v
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
+set_global_assignment -name POWER_USE_INPUT_FILES ON
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME ADD_1 -section_id eda_simulation
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name POWER_USE_PVA ON
+set_global_assignment -name VERILOG_FILE SM_pipelined.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_INPUT_FILE_NAME simulation/qsim/CPUProject.msim.vcd -section_id cpuproject.msim.vcd
+set_instance_assignment -name POWER_READ_INPUT_FILE cpuproject.msim.vcd -to ADD_1
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/CPUProject.qws b/CPUProject.qws
deleted file mode 100644
index adffd16..0000000
Binary files a/CPUProject.qws and /dev/null differ
diff --git a/SM_pipelined.v b/SM_pipelined.v
new file mode 100644
index 0000000..d1a849a
--- /dev/null
+++ b/SM_pipelined.v
@@ -0,0 +1,27 @@
+module SM_pipelined (CLK, RST, E2, EXEC1, EXEC2);
+
+input CLK;
+input RST;
+input E2;
+output EXEC1;
+output EXEC2;
+
+reg s = 0;
+
+assign EXEC1 = ~s;
+assign EXEC2 = s;
+
+always @(posedge CLK) begin
+	if(!RST)
+		if(!s)
+			if(E2)
+				s <= 1;
+			else
+				s <= 0;
+		else
+			s <= 0;
+	else
+		s <= 0;
+end
+
+endmodule
diff --git a/SM_pipelined.v.bak b/SM_pipelined.v.bak
new file mode 100644
index 0000000..2fd8735
--- /dev/null
+++ b/SM_pipelined.v.bak
@@ -0,0 +1,26 @@
+module SM_piplined (CLK, RST, E2, EXEC1, EXEC2);
+
+input CLK;
+input RST;
+input E2;
+output EXEC1;
+output EXEC2;
+
+reg s;
+
+always @(posedge CLK) begin
+	if(!RST)
+		if(!s)
+			if(E2)
+				s = 1'b1;
+			else ;
+		else
+			s = 1'b0;
+	else
+		s = 1'b0;
+end
+
+assign EXEC1 = ~s;
+assign EXEC2 = s;
+
+endmodule