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https://github.com/supleed2/ELEC40006-P1-CW.git
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86 lines
4.9 KiB
Verilog
86 lines
4.9 KiB
Verilog
module DECODE
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(
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input [15:0] instr,
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input FETCH,
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input EXEC1,
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input EXEC2,
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input COND_result,
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output R0_count,
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output R0_en,
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output R1_en,
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output R2_en,
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output R3_en,
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output R4_en,
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output R5_en,
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output R6_en,
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output R7_en,
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output [2:0] s1,
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output [2:0] s2,
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output [2:0] s3,
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output s4,
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output RAMd_wren,
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output RAMd_en,
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output RAMi_en,
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output ALU_en,
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output E2,
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output stack_en,
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output stack_rst,
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output stack_rw,
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output s5
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);
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wire msb = instr[15]; //MSB of the instruction word
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wire ls = instr[14]; //LDA or STA bit
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wire [2:0] Rls = instr[13:11]; //Register in the LDA/STA operation
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wire [10:0] addr = instr[10:0]; //Memory address in the LDA/STA operation
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wire [5:0] op = instr[14:9]; //Opcode in regular instructions
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wire [2:0] Rd = instr[8:6]; //Destination register in command
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wire [2:0] Rs1 = instr[5:3]; //Source register 1 in command
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wire [2:0] Rs2 = instr[2:0]; //Source register 2 in command
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//Different opcodes (refer to documentation):
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wire LDA = msb & ~ls;
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wire STA = msb & ls;
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wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
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wire JCX = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
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wire MUL = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
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wire MLA = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
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wire MLS = ~msb & ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
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wire PSH = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
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wire POP = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
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wire LDR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0];
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wire STR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
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wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
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wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
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assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP));
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assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
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assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]);
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assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]);
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assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & Rd[0]);
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assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]);
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assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & Rd[0]);
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assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & ~Rd[0]);
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assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & Rd[0]);
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assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]);
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assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]);
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assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]);
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assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]);
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assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]);
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assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]);
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assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[2]);
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assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[1]);
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assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[0]);
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assign s4 = ~(LDA | LDR);
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assign RAMd_wren = EXEC1 & (STA | STR);
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assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR);
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assign RAMi_en = FETCH;
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assign ALU_en = LDA | STA;
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assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR);
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assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP);
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assign stack_rst = STP;
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assign stack_rw = EXEC1 & PSH;
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assign s5 = EXEC1 & (STR | LDR);
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endmodule
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