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Working on initial design
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Kacper
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CPUProject.bdf
279
CPUProject.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
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/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,115 +16,196 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
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||||
*/
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@ -38,16 +38,17 @@
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
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set_global_assignment -name TOP_LEVEL_ENTITY reg_file
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name BDF_FILE CPUProject.bdf
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_global_assignment -name BDF_FILE CPUProject.bdf
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set_global_assignment -name BDF_FILE reg_file.bdf
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set_global_assignment -name BDF_FILE mux_8x16.bdf
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178
Waveform.vwf
178
Waveform.vwf
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@ -1,178 +0,0 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work CPUProject.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
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vcd file -direction CPUProject.msim.vcd
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vcd add -internal CPUProject_vlg_vec_tst/*
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vcd add -internal CPUProject_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work CPUProject.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
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vcd file -direction CPUProject.msim.vcd
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vcd add -internal CPUProject_vlg_vec_tst/*
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vcd add -internal CPUProject_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
|
||||
HEADER
|
||||
{
|
||||
VERSION = 1;
|
||||
TIME_UNIT = ns;
|
||||
DATA_OFFSET = 0.0;
|
||||
DATA_DURATION = 1000.0;
|
||||
SIMULATION_TIME = 0.0;
|
||||
GRID_PHASE = 0.0;
|
||||
GRID_PERIOD = 10.0;
|
||||
GRID_DUTY_CYCLE = 50;
|
||||
}
|
||||
|
||||
SIGNAL("X")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("Y")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("Z")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("X")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 50;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("Y")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 25;
|
||||
LEVEL 0 FOR 20.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("Z")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "X";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Y";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Z";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
784
mux_8x16.bdf
Normal file
784
mux_8x16.bdf
Normal file
|
|
@ -0,0 +1,784 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
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|
||||
(rect 104 64 272 80)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "s0" (rect 5 0 17 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
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||||
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|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
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|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
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|
||||
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|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
(pt 168 8)
|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
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|
||||
)
|
||||
(pin
|
||||
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|
||||
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|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
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|
||||
(pt 168 8)
|
||||
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|
||||
(line (pt 84 12)(pt 109 12))
|
||||
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|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 176 272 192)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in0[15..0]" (rect 5 0 52 12)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 208 272 224)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in1[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 296 272 312)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in2[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 328 272 344)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in3[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 416 272 432)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in4[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 448 272 464)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in5[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 536 272 552)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in6[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 104 568 272 584)
|
||||
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
|
||||
(text "in7[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 872 192 1048 208)
|
||||
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
|
||||
(text "result[15..0]" (rect 90 0 149 12)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 312 272 424 360)
|
||||
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
|
||||
(text "inst5" (rect 3 77 25 94)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 44 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 56 88)
|
||||
(input)
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(line (pt 56 88)(pt 56 72))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 44 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 112 48)
|
||||
(output)
|
||||
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
|
||||
(line (pt 68 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
)
|
||||
(drawing
|
||||
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
|
||||
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
|
||||
(line (pt 68 64)(pt 68 32))
|
||||
(line (pt 44 80)(pt 44 16))
|
||||
(line (pt 44 16)(pt 68 32))
|
||||
(line (pt 44 80)(pt 68 64))
|
||||
)
|
||||
(annotation_block (parameter)(rect 424 272 448 288))
|
||||
)
|
||||
(symbol
|
||||
(rect 312 392 424 480)
|
||||
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
|
||||
(text "inst6" (rect 3 77 25 94)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 44 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 56 88)
|
||||
(input)
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(line (pt 56 88)(pt 56 72))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 44 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 112 48)
|
||||
(output)
|
||||
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
|
||||
(line (pt 68 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
)
|
||||
(drawing
|
||||
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
|
||||
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
|
||||
(line (pt 68 64)(pt 68 32))
|
||||
(line (pt 44 80)(pt 44 16))
|
||||
(line (pt 44 16)(pt 68 32))
|
||||
(line (pt 44 80)(pt 68 64))
|
||||
)
|
||||
(annotation_block (parameter)(rect 424 392 448 408))
|
||||
)
|
||||
(symbol
|
||||
(rect 312 512 424 600)
|
||||
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
|
||||
(text "inst7" (rect 3 77 25 94)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 44 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 56 88)
|
||||
(input)
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(line (pt 56 88)(pt 56 72))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 44 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
(pt 112 48)
|
||||
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|
||||
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|
||||
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|
||||
(line (pt 68 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
)
|
||||
(drawing
|
||||
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(line (pt 68 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
)
|
||||
(drawing
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
(parameter
|
||||
"WIDTH"
|
||||
"16"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(bus)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(junction (pt 296 376))
|
||||
(junction (pt 296 256))
|
||||
(junction (pt 512 256))
|
||||
113
mux_8x16.bsf
Normal file
113
mux_8x16.bsf
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 200 240)
|
||||
(text "mux_8x16" (rect 5 0 67 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 203 24 220)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "s0" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "s0" (rect 21 27 35 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "s1" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "s1" (rect 21 43 35 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "s2" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "s2" (rect 21 59 35 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "in0[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in0[15..0]" (rect 21 75 78 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "in1[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in1[15..0]" (rect 21 91 78 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "in2[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in2[15..0]" (rect 21 107 78 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "in3[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in3[15..0]" (rect 21 123 78 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "in4[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in4[15..0]" (rect 21 139 78 158)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "in5[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in5[15..0]" (rect 21 155 78 174)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "in6[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in6[15..0]" (rect 21 171 78 190)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "in7[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "in7[15..0]" (rect 21 187 78 206)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "result[15..0]" (rect 0 0 71 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "result[15..0]" (rect 92 27 163 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 208))
|
||||
)
|
||||
)
|
||||
1565
reg_file.bdf
Normal file
1565
reg_file.bdf
Normal file
File diff suppressed because it is too large
Load diff
211
reg_file.bsf
Normal file
211
reg_file.bsf
Normal file
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 224 368)
|
||||
(text "reg_file" (rect 5 0 49 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 331 24 348)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLK" (rect 0 0 23 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLK" (rect 21 27 44 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "R0_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R0_en" (rect 21 43 58 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "R0_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R0_in[15..0]" (rect 21 59 94 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "R0_count" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R0_count" (rect 21 75 76 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "R1_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R1_in[15..0]" (rect 21 91 94 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "R1_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R1_en" (rect 21 107 58 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "R2_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R2_in[15..0]" (rect 21 123 94 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "R2_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R2_en" (rect 21 139 58 158)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "R3_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R3_in[15..0]" (rect 21 155 94 174)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 160)(pt 16 160)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "R3_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R3_en" (rect 21 171 58 190)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 176)(pt 16 176))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "R4_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R4_in[15..0]" (rect 21 187 94 206)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 192)(pt 16 192)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "R4_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R4_en" (rect 21 203 58 222)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "R5_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R5_in[15..0]" (rect 21 219 94 238)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 240)
|
||||
(input)
|
||||
(text "R5_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R5_en" (rect 21 235 58 254)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 240)(pt 16 240))
|
||||
)
|
||||
(port
|
||||
(pt 0 256)
|
||||
(input)
|
||||
(text "R6_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R6_in[15..0]" (rect 21 251 94 270)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 256)(pt 16 256)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 272)
|
||||
(input)
|
||||
(text "R6_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R6_en" (rect 21 267 58 286)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 272)(pt 16 272))
|
||||
)
|
||||
(port
|
||||
(pt 0 288)
|
||||
(input)
|
||||
(text "R7_in[15..0]" (rect 0 0 73 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R7_in[15..0]" (rect 21 283 94 302)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 288)(pt 16 288)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 304)
|
||||
(input)
|
||||
(text "R7_en" (rect 0 0 37 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R7_en" (rect 21 299 58 318)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 304)(pt 16 304))
|
||||
)
|
||||
(port
|
||||
(pt 208 32)
|
||||
(output)
|
||||
(text " R0_out[15..0]" (rect 0 0 84 19)(font "Intel Clear" (font_size 8)))
|
||||
(text " R0_out[15..0]" (rect 103 27 187 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 48)
|
||||
(output)
|
||||
(text "R1_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R1_out[15..0]" (rect 106 43 187 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 48)(pt 192 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 64)
|
||||
(output)
|
||||
(text "R2_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R2_out[15..0]" (rect 106 59 187 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 64)(pt 192 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 80)
|
||||
(output)
|
||||
(text "R3_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R3_out[15..0]" (rect 106 75 187 94)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 80)(pt 192 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 96)
|
||||
(output)
|
||||
(text "R4_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R4_out[15..0]" (rect 106 91 187 110)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 96)(pt 192 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 112)
|
||||
(output)
|
||||
(text "R5_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R5_out[15..0]" (rect 106 107 187 126)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 112)(pt 192 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 128)
|
||||
(output)
|
||||
(text "R6_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R6_out[15..0]" (rect 106 123 187 142)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 128)(pt 192 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 144)
|
||||
(output)
|
||||
(text "R7_out[15..0]" (rect 0 0 81 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "R7_out[15..0]" (rect 106 139 187 158)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 208 144)(pt 192 144)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 192 336))
|
||||
)
|
||||
)
|
||||
Loading…
Reference in a new issue