mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-09-19 20:26:18 +00:00
Added LDR and STR to alu and set up data paths
Decoder changes remaining
This commit is contained in:
parent
a249245102
commit
a1cf89e644
316
ALU_top.bdf
316
ALU_top.bdf
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@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
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@ -148,9 +148,25 @@ https://fpgasoftware.intel.com/eula.
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@ -166,7 +182,7 @@ https://fpgasoftware.intel.com/eula.
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@ -182,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
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@ -198,7 +214,7 @@ https://fpgasoftware.intel.com/eula.
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@ -214,7 +230,7 @@ https://fpgasoftware.intel.com/eula.
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@ -230,7 +246,7 @@ https://fpgasoftware.intel.com/eula.
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|
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@ -246,9 +262,25 @@ https://fpgasoftware.intel.com/eula.
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@ -261,7 +293,7 @@ https://fpgasoftware.intel.com/eula.
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@ -297,9 +329,9 @@ https://fpgasoftware.intel.com/eula.
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@ -357,110 +389,65 @@ https://fpgasoftware.intel.com/eula.
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|
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@ -486,67 +473,136 @@ https://fpgasoftware.intel.com/eula.
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
)
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
)
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||||
(junction (pt 752 456))
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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66
ALU_top.bsf
66
ALU_top.bsf
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@ -21,7 +21,7 @@ https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.2"))
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||||
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||||
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||||
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||||
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||||
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||||
(port
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||||
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@ -76,60 +76,74 @@ https://fpgasoftware.intel.com/eula.
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|||
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||||
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||||
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||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|||
381
CPUProject.bdf
381
CPUProject.bdf
|
|
@ -791,6 +791,22 @@ https://fpgasoftware.intel.com/eula.
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|
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|
|
@ -1568,7 +1584,7 @@ https://fpgasoftware.intel.com/eula.
|
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|
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|
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@ -1623,61 +1639,75 @@ https://fpgasoftware.intel.com/eula.
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|
||||
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@ -1862,17 +1892,59 @@ https://fpgasoftware.intel.com/eula.
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|
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|
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|
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(parameter
|
||||
"WIDTH"
|
||||
"11"
|
||||
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|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
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|
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|
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|
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|
||||
|
|
@ -2541,22 +2613,6 @@ https://fpgasoftware.intel.com/eula.
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|
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|
|
@ -2727,11 +2783,71 @@ https://fpgasoftware.intel.com/eula.
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|
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|
|
@ -2743,74 +2859,11 @@ https://fpgasoftware.intel.com/eula.
|
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||||
(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
|
||||
(pt 1184 400)
|
||||
(pt 1232 400)
|
||||
)
|
||||
(connector
|
||||
(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
|
||||
(pt 1184 416)
|
||||
(pt 1232 416)
|
||||
)
|
||||
(connector
|
||||
(text "jumpflags[7..0]" (rect 1184 416 1254 433)(font "Intel Clear" ))
|
||||
(pt 1184 432)
|
||||
|
|
@ -2818,9 +2871,19 @@ https://fpgasoftware.intel.com/eula.
|
|||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "MUL_res[31..0]" (rect 1184 432 1255 449)(font "Intel Clear" ))
|
||||
(pt 1184 448)
|
||||
(pt 1232 448)
|
||||
(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
|
||||
(pt 1184 416)
|
||||
(pt 1232 416)
|
||||
)
|
||||
(connector
|
||||
(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
|
||||
(pt 1184 400)
|
||||
(pt 1232 400)
|
||||
)
|
||||
(connector
|
||||
(text "mul2[15..0]" (rect 1192 352 1246 369)(font "Intel Clear" ))
|
||||
(pt 1184 368)
|
||||
(pt 1232 368)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
|
|
@ -2830,21 +2893,89 @@ https://fpgasoftware.intel.com/eula.
|
|||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul2[15..0]" (rect 1192 352 1246 369)(font "Intel Clear" ))
|
||||
(pt 1184 368)
|
||||
(pt 1232 368)
|
||||
(text "MUL_res[31..0]" (rect 1184 448 1255 465)(font "Intel Clear" ))
|
||||
(pt 1184 464)
|
||||
(pt 1232 464)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul1[15..0]" (rect 1448 360 1502 377)(font "Intel Clear" ))
|
||||
(pt 1512 376)
|
||||
(pt 1440 376)
|
||||
(text "CLK" (rect 882 464 902 481)(font "Intel Clear" ))
|
||||
(pt 928 480)
|
||||
(pt 872 480)
|
||||
)
|
||||
(connector
|
||||
(text "RAMd_out[15..0]" (rect 870 448 950 465)(font "Intel Clear" ))
|
||||
(pt 928 464)
|
||||
(pt 872 464)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "mul2[15..0]" (rect 1448 376 1502 393)(font "Intel Clear" ))
|
||||
(pt 1512 392)
|
||||
(pt 1440 392)
|
||||
(pt 872 -104)
|
||||
(pt 872 24)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 872 24)
|
||||
(pt 872 56)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "instr[10..0]" (rect 904 40 953 57)(font "Intel Clear" ))
|
||||
(pt 872 56)
|
||||
(pt 968 56)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "instr[15..0]" (rect 827 8 876 25)(font "Intel Clear" ))
|
||||
(pt 872 24)
|
||||
(pt 816 24)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "memaddr[10..0]" (rect 880 72 955 89)(font "Intel Clear" ))
|
||||
(pt 968 88)
|
||||
(pt 872 88)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "memaddr[10..0]" (rect 1192 432 1267 449)(font "Intel Clear" ))
|
||||
(pt 1184 448)
|
||||
(pt 1232 448)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1080 72)
|
||||
(pt 1088 72)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 872 224)
|
||||
(pt 936 224)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1088 72)
|
||||
(pt 1088 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1088 152)
|
||||
(pt 872 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 872 224)
|
||||
(pt 872 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1024 112)
|
||||
(pt 1024 136)
|
||||
)
|
||||
(connector
|
||||
(text "memaddr[10..0]" (rect 1448 392 1523 409)(font "Intel Clear" ))
|
||||
(pt 1512 408)
|
||||
(pt 1440 408)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt 856 192))
|
||||
|
|
@ -2872,5 +3003,5 @@ https://fpgasoftware.intel.com/eula.
|
|||
(junction (pt 560 496))
|
||||
(junction (pt 576 512))
|
||||
(junction (pt 1416 496))
|
||||
(junction (pt 872 24))
|
||||
(junction (pt 536 192))
|
||||
(junction (pt 872 24))
|
||||
|
|
|
|||
56
alu.bsf
56
alu.bsf
|
|
@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
|
|||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 232 192)
|
||||
(rect 16 16 248 224)
|
||||
(text "alu" (rect 5 0 15 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 160 20 172)(font "Arial" ))
|
||||
(text "inst" (rect 8 192 20 204)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
|
|
@ -81,48 +81,62 @@ https://fpgasoftware.intel.com/eula.
|
|||
(line (pt 0 144)(pt 16 144)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 32)
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "memdatain[15..0]" (rect 0 0 67 12)(font "Arial" ))
|
||||
(text "memdatain[15..0]" (rect 21 155 88 167)(font "Arial" ))
|
||||
(line (pt 0 160)(pt 16 160)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 32)
|
||||
(output)
|
||||
(text "mul1[15..0]" (rect 0 0 41 12)(font "Arial" ))
|
||||
(text "mul1[15..0]" (rect 154 27 195 39)(font "Arial" ))
|
||||
(line (pt 216 32)(pt 200 32)(line_width 3))
|
||||
(text "mul1[15..0]" (rect 170 27 211 39)(font "Arial" ))
|
||||
(line (pt 232 32)(pt 216 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 48)
|
||||
(pt 232 48)
|
||||
(output)
|
||||
(text "mul2[15..0]" (rect 0 0 42 12)(font "Arial" ))
|
||||
(text "mul2[15..0]" (rect 153 43 195 55)(font "Arial" ))
|
||||
(line (pt 216 48)(pt 200 48)(line_width 3))
|
||||
(text "mul2[15..0]" (rect 169 43 211 55)(font "Arial" ))
|
||||
(line (pt 232 48)(pt 216 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 64)
|
||||
(pt 232 64)
|
||||
(output)
|
||||
(text "Rout[15..0]" (rect 0 0 43 12)(font "Arial" ))
|
||||
(text "Rout[15..0]" (rect 152 59 195 71)(font "Arial" ))
|
||||
(line (pt 216 64)(pt 200 64)(line_width 3))
|
||||
(text "Rout[15..0]" (rect 168 59 211 71)(font "Arial" ))
|
||||
(line (pt 232 64)(pt 216 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 80)
|
||||
(pt 232 80)
|
||||
(output)
|
||||
(text "jump" (rect 0 0 18 12)(font "Arial" ))
|
||||
(text "jump" (rect 177 75 195 87)(font "Arial" ))
|
||||
(line (pt 216 80)(pt 200 80)(line_width 1))
|
||||
(text "jump" (rect 193 75 211 87)(font "Arial" ))
|
||||
(line (pt 232 80)(pt 216 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 96)
|
||||
(pt 232 96)
|
||||
(output)
|
||||
(text "carry" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "carry" (rect 173 91 195 103)(font "Arial" ))
|
||||
(line (pt 216 96)(pt 200 96)(line_width 1))
|
||||
(text "carry" (rect 189 91 211 103)(font "Arial" ))
|
||||
(line (pt 232 96)(pt 216 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 112)
|
||||
(pt 232 112)
|
||||
(output)
|
||||
(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
|
||||
(text "jumpflags[7..0]" (rect 138 107 195 119)(font "Arial" ))
|
||||
(line (pt 216 112)(pt 200 112)(line_width 3))
|
||||
(text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" ))
|
||||
(line (pt 232 112)(pt 216 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 232 128)
|
||||
(output)
|
||||
(text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" ))
|
||||
(text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" ))
|
||||
(line (pt 232 128)(pt 216 128)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 200 160)(line_width 1))
|
||||
(rectangle (rect 16 16 216 192)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
|
|||
19
alu.v
19
alu.v
|
|
@ -1,13 +1,14 @@
|
|||
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags);
|
||||
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr);
|
||||
|
||||
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
|
||||
input signed [15:0] Rd; // input destination register
|
||||
input signed [15:0] Rs1; // input source register 1
|
||||
input signed [15:0] Rs2; // input source register 2
|
||||
input signed [15:0] Rd; // input destination register
|
||||
input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
|
||||
input signed [31:0] mulresult; // 32-bit result from multiplier
|
||||
input exec2; // Input from state machine to indicate when to take in result from multiplication
|
||||
input [15:0] stackout; // input from stack to be fed back to registers
|
||||
input signed [15:0] memdatain; // input data from RAMd
|
||||
|
||||
output reg signed [15:0] mul1; // first number to be multiplied
|
||||
output reg signed [15:0] mul2; // second number to be multiplied
|
||||
|
|
@ -15,6 +16,7 @@ output signed [15:0] Rout; // value to be saved to destination register
|
|||
output jump; // tells decoder whether Jump condition is true
|
||||
output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
|
||||
output [7:0] jumpflags;
|
||||
output reg [10:0] memaddr; // address to load data from / store data to RAMd
|
||||
|
||||
reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
|
||||
assign Rout = alusum [15:0];
|
||||
|
|
@ -164,8 +166,17 @@ always @(opcode, mulresult)
|
|||
|
||||
6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1)
|
||||
6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack)
|
||||
6'b101010: ;
|
||||
6'b101011: ;
|
||||
6'b101010: begin // LDR Indirect Load (Rd = Mem[Rs1])
|
||||
if(!exec2) begin
|
||||
memaddr = Rs1[10:0];
|
||||
end
|
||||
else begin
|
||||
alusum = {1'b0, memdatain};
|
||||
end
|
||||
end
|
||||
6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
|
||||
memaddr = Rd[10:0];
|
||||
end
|
||||
|
||||
6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
|
||||
6'b111111: alusum = {1'b0, 16'h0000}; // STP Stop (Program Ends)
|
||||
|
|
|
|||
Loading…
Reference in a new issue