Added LDR and STR to alu and set up data paths

Decoder changes remaining
This commit is contained in:
Aadi Desai 2020-06-10 14:02:15 +01:00
parent a249245102
commit a1cf89e644
5 changed files with 532 additions and 306 deletions

View file

@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
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@ -21,7 +21,7 @@ https://fpgasoftware.intel.com/eula.
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(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 1080 24 1112 48))
)
(connector
(pt 856 192)
(pt 936 192)
(bus)
)
(connector
(text "instr[10..0]" (rect 882 208 931 225)(font "Intel Clear" ))
(pt 936 224)
(pt 872 224)
(bus)
)
(connector
(text "RAMd_en" (rect 890 272 937 289)(font "Intel Clear" ))
(pt 936 288)
@ -2541,22 +2613,6 @@ https://fpgasoftware.intel.com/eula.
(pt 560 120)
(pt 600 120)
)
(connector
(pt 872 24)
(pt 872 224)
(bus)
)
(connector
(text "instr[15..0]" (rect 826 8 875 25)(font "Intel Clear" ))
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(bus)
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(connector
(pt 872 -104)
(pt 872 24)
(bus)
)
(connector
(text "instr[15..0]" (rect 882 -120 931 -103)(font "Intel Clear" ))
(pt 872 -104)
@ -2727,11 +2783,71 @@ https://fpgasoftware.intel.com/eula.
(pt 1440 360)
(bus)
)
(connector
(pt 1256 336)
(pt 1248 336)
(bus)
)
(connector
(text "mul1[15..0]" (rect 1448 360 1502 377)(font "Intel Clear" ))
(pt 1512 376)
(pt 1440 376)
(bus)
)
(connector
(text "mul2[15..0]" (rect 1448 376 1502 393)(font "Intel Clear" ))
(pt 1512 392)
(pt 1440 392)
(bus)
)
(connector
(pt 856 592)
(pt 856 400)
(bus)
)
(connector
(text "ALU_en" (rect 882 336 919 353)(font "Intel Clear" ))
(pt 872 352)
(pt 928 352)
)
(connector
(pt 856 368)
(pt 928 368)
(bus)
)
(connector
(text "Rs2[15..0]" (rect 816 368 863 385)(font "Intel Clear" ))
(pt 816 384)
(pt 928 384)
(bus)
)
(connector
(pt 856 400)
(pt 928 400)
(bus)
)
(connector
(text "instr[14..9]" (rect 882 400 931 417)(font "Intel Clear" ))
(pt 872 416)
(pt 928 416)
(bus)
)
(connector
(text "EXEC2" (rect 882 416 913 433)(font "Intel Clear" ))
(pt 872 432)
(pt 928 432)
)
(connector
(text "stack_out[15..0]" (rect 872 432 947 449)(font "Intel Clear" ))
(pt 872 448)
(pt 928 448)
(bus)
)
(connector
(pt 1248 336)
(pt 1248 384)
(bus)
)
(connector
(pt 856 176)
(pt 856 192)
@ -2743,74 +2859,11 @@ https://fpgasoftware.intel.com/eula.
(bus)
)
(connector
(text "ALU_en" (rect 890 336 927 353)(font "Intel Clear" ))
(pt 880 352)
(pt 936 352)
)
(connector
(pt 856 368)
(pt 936 368)
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(connector
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(bus)
)
(connector
(text "EXEC2" (rect 890 416 921 433)(font "Intel Clear" ))
(pt 880 432)
(pt 936 432)
)
(connector
(text "stack_out[15..0]" (rect 880 432 955 449)(font "Intel Clear" ))
(pt 880 448)
(pt 936 448)
(bus)
)
(connector
(text "CLK" (rect 890 448 910 465)(font "Intel Clear" ))
(pt 880 464)
(pt 936 464)
)
(connector
(pt 1256 336)
(pt 1248 336)
(bus)
)
(connector
(pt 1248 336)
(pt 1248 384)
(bus)
)
(connector
(text "ALU_out[15..0]" (rect 1186 368 1256 385)(font "Intel Clear" ))
(text "ALU_out[15..0]" (rect 1178 368 1248 385)(font "Intel Clear" ))
(pt 1184 384)
(pt 1248 384)
(bus)
)
(connector
(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
(pt 1184 400)
(pt 1232 400)
)
(connector
(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
(pt 1184 416)
(pt 1232 416)
)
(connector
(text "jumpflags[7..0]" (rect 1184 416 1254 433)(font "Intel Clear" ))
(pt 1184 432)
@ -2818,9 +2871,19 @@ https://fpgasoftware.intel.com/eula.
(bus)
)
(connector
(text "MUL_res[31..0]" (rect 1184 432 1255 449)(font "Intel Clear" ))
(pt 1184 448)
(pt 1232 448)
(text "CARRY" (rect 1186 400 1221 417)(font "Intel Clear" ))
(pt 1184 416)
(pt 1232 416)
)
(connector
(text "COND" (rect 1194 384 1223 401)(font "Intel Clear" ))
(pt 1184 400)
(pt 1232 400)
)
(connector
(text "mul2[15..0]" (rect 1192 352 1246 369)(font "Intel Clear" ))
(pt 1184 368)
(pt 1232 368)
(bus)
)
(connector
@ -2830,21 +2893,89 @@ https://fpgasoftware.intel.com/eula.
(bus)
)
(connector
(text "mul2[15..0]" (rect 1192 352 1246 369)(font "Intel Clear" ))
(pt 1184 368)
(pt 1232 368)
(text "MUL_res[31..0]" (rect 1184 448 1255 465)(font "Intel Clear" ))
(pt 1184 464)
(pt 1232 464)
(bus)
)
(connector
(text "mul1[15..0]" (rect 1448 360 1502 377)(font "Intel Clear" ))
(pt 1512 376)
(pt 1440 376)
(text "CLK" (rect 882 464 902 481)(font "Intel Clear" ))
(pt 928 480)
(pt 872 480)
)
(connector
(text "RAMd_out[15..0]" (rect 870 448 950 465)(font "Intel Clear" ))
(pt 928 464)
(pt 872 464)
(bus)
)
(connector
(text "mul2[15..0]" (rect 1448 376 1502 393)(font "Intel Clear" ))
(pt 1512 392)
(pt 1440 392)
(pt 872 -104)
(pt 872 24)
(bus)
)
(connector
(pt 872 24)
(pt 872 56)
(bus)
)
(connector
(text "instr[10..0]" (rect 904 40 953 57)(font "Intel Clear" ))
(pt 872 56)
(pt 968 56)
(bus)
)
(connector
(text "instr[15..0]" (rect 827 8 876 25)(font "Intel Clear" ))
(pt 872 24)
(pt 816 24)
(bus)
)
(connector
(text "memaddr[10..0]" (rect 880 72 955 89)(font "Intel Clear" ))
(pt 968 88)
(pt 872 88)
(bus)
)
(connector
(text "memaddr[10..0]" (rect 1192 432 1267 449)(font "Intel Clear" ))
(pt 1184 448)
(pt 1232 448)
(bus)
)
(connector
(pt 1080 72)
(pt 1088 72)
(bus)
)
(connector
(pt 872 224)
(pt 936 224)
(bus)
)
(connector
(pt 1088 72)
(pt 1088 152)
(bus)
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(connector
(pt 1088 152)
(pt 872 152)
(bus)
)
(connector
(pt 872 224)
(pt 872 152)
(bus)
)
(connector
(pt 1024 112)
(pt 1024 136)
)
(connector
(text "memaddr[10..0]" (rect 1448 392 1523 409)(font "Intel Clear" ))
(pt 1512 408)
(pt 1440 408)
(bus)
)
(junction (pt 856 192))
@ -2872,5 +3003,5 @@ https://fpgasoftware.intel.com/eula.
(junction (pt 560 496))
(junction (pt 576 512))
(junction (pt 1416 496))
(junction (pt 872 24))
(junction (pt 536 192))
(junction (pt 872 24))

56
alu.bsf
View file

@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 232 192)
(rect 16 16 248 224)
(text "alu" (rect 5 0 15 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" ))
(text "inst" (rect 8 192 20 204)(font "Arial" ))
(port
(pt 0 32)
(input)
@ -81,48 +81,62 @@ https://fpgasoftware.intel.com/eula.
(line (pt 0 144)(pt 16 144)(line_width 3))
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(port
(pt 216 32)
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(text "Rout[15..0]" (rect 152 59 195 71)(font "Arial" ))
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(text "Rout[15..0]" (rect 168 59 211 71)(font "Arial" ))
(line (pt 232 64)(pt 216 64)(line_width 3))
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(port
(pt 216 80)
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(text "jump" (rect 177 75 195 87)(font "Arial" ))
(line (pt 216 80)(pt 200 80)(line_width 1))
(text "jump" (rect 193 75 211 87)(font "Arial" ))
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(port
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(pt 232 96)
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(text "carry" (rect 0 0 22 12)(font "Arial" ))
(text "carry" (rect 173 91 195 103)(font "Arial" ))
(line (pt 216 96)(pt 200 96)(line_width 1))
(text "carry" (rect 189 91 211 103)(font "Arial" ))
(line (pt 232 96)(pt 216 96)(line_width 1))
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(pt 216 112)
(pt 232 112)
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(text "jumpflags[7..0]" (rect 0 0 57 12)(font "Arial" ))
(text "jumpflags[7..0]" (rect 138 107 195 119)(font "Arial" ))
(line (pt 216 112)(pt 200 112)(line_width 3))
(text "jumpflags[7..0]" (rect 154 107 211 119)(font "Arial" ))
(line (pt 232 112)(pt 216 112)(line_width 3))
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(pt 232 128)
(output)
(text "memaddr[10..0]" (rect 0 0 62 12)(font "Arial" ))
(text "memaddr[10..0]" (rect 149 123 211 135)(font "Arial" ))
(line (pt 232 128)(pt 216 128)(line_width 3))
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(drawing
(rectangle (rect 16 16 200 160)(line_width 1))
(rectangle (rect 16 16 216 192)(line_width 1))
)
)

19
alu.v
View file

@ -1,13 +1,14 @@
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags);
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr);
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
input signed [15:0] Rd; // input destination register
input signed [15:0] Rs1; // input source register 1
input signed [15:0] Rs2; // input source register 2
input signed [15:0] Rd; // input destination register
input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
input signed [31:0] mulresult; // 32-bit result from multiplier
input exec2; // Input from state machine to indicate when to take in result from multiplication
input [15:0] stackout; // input from stack to be fed back to registers
input signed [15:0] memdatain; // input data from RAMd
output reg signed [15:0] mul1; // first number to be multiplied
output reg signed [15:0] mul2; // second number to be multiplied
@ -15,6 +16,7 @@ output signed [15:0] Rout; // value to be saved to destination register
output jump; // tells decoder whether Jump condition is true
output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
output [7:0] jumpflags;
output reg [10:0] memaddr; // address to load data from / store data to RAMd
reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
assign Rout = alusum [15:0];
@ -164,8 +166,17 @@ always @(opcode, mulresult)
6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1)
6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack)
6'b101010: ;
6'b101011: ;
6'b101010: begin // LDR Indirect Load (Rd = Mem[Rs1])
if(!exec2) begin
memaddr = Rs1[10:0];
end
else begin
alusum = {1'b0, memdatain};
end
end
6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
memaddr = Rd[10:0];
end
6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
6'b111111: alusum = {1'b0, 16'h0000}; // STP Stop (Program Ends)