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Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available

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ben 2020-05-29 09:47:44 -07:00
parent 3f0c91b0ff
commit 5d6c9803fc
11 changed files with 918 additions and 305 deletions
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3
CPUProject.qsf
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@ -57,8 +57,9 @@ set_global_assignment -name BDF_FILE SM.bdf
set_global_assignment -name VERILOG_FILE DECODE.v
set_global_assignment -name MIF_FILE data.mif
set_global_assignment -name MIF_FILE instr.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE mul16.bdf
set_global_assignment -name QIP_FILE LUT.qip
set_global_assignment -name VERILOG_FILE min.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

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CPUProject.qws
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LUT.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 256 120)
(text "LUT" (rect 102 0 129 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 8 149 31)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[7..0]" (rect 4 40 148 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 3))
)
(port
(pt 0 96)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 72 51 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 176 96))
)
(port
(pt 256 32)
(output)
(text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "q_a[15..0]" (rect 158 8 251 31)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
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(text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "q_b[15..0]" (rect 159 40 251 63)(font "Arial" (font_size 8)))
(line (pt 256 64)(pt 192 64)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 127 -1 253 231)(font "Arial" )(vertical))
(text "RAM" (rect 148 -22 243 169)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 40 99 239 219)(font "Arial" ))
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5
LUT.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ROM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LUT.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "LUT.bsf"]

229
LUT.v Normal file
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@ -0,0 +1,229 @@
// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: LUT.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
// ************************************************************
//Copyright (C) 2019 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module LUT (
address_a,
address_b,
clock,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "LUTSquares.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "LUTSquares.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "LUTSquares.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LUT_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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min.bsf Normal file
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@ -0,0 +1,58 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 128)
(text "min" (rect 5 0 19 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
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)
(drawing
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)
)

7
min.v Normal file
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@ -0,0 +1,7 @@
module min(sign, a, b, num);
input sign;
input [7:0] a;
input [7:0] b;
output [7:0] num;
assign num = sign ? a[7:0]:b[7:0];
endmodule

12
min.v.bak Normal file
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@ -0,0 +1,12 @@
module MIN(
input sign,
input a[7..0],
input b[7..0],
output [7..0] num;
);
assign num = sign ? a[7..0]:b[7..0]
endmodule

444
mul16.bdf
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@ -24,7 +24,7 @@ https://fpgasoftware.intel.com/eula.
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@ -40,7 +40,7 @@ https://fpgasoftware.intel.com/eula.
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@ -307,10 +223,10 @@ https://fpgasoftware.intel.com/eula.
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@ -650,32 +727,135 @@ https://fpgasoftware.intel.com/eula.
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335
mul8.bdf
View file

@ -52,6 +52,22 @@ https://fpgasoftware.intel.com/eula.
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(text "q[LPM_WIDTH-1..0]" (rect 80 41 188 55)(font "Arial" (font_size 8)))
(text "q[]" (rect 80 41 94 55)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 112 48)(line_width 3))
(text "num[7..0]" (rect 0 0 47 12)(font "Arial" ))
(text "num[7..0]" (rect 100 27 147 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(parameter
"LPM_ADDRESS_CONTROL"
"\"UNREGISTERED\""
"Should the address and control ports be registered?"
"\"REGISTERED\"" "\"UNREGISTERED\""
)
(parameter
"LPM_FILE"
"\"LUTSquares.mif\""
"File containing initial contents of memory array"
(type "PARAMETER_UNKNOWN") )
(parameter
"LPM_NUMWORDS"
"256"
"Number of memory words, default is 2^LPM_WIDTHAD"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_OUTDATA"
"\"UNREGISTERED\""
"Should the output data be registered?"
"\"REGISTERED\"" "\"UNREGISTERED\""
)
(parameter
"LPM_WIDTH"
"16"
"Data width in bits, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_WIDTHAD"
"8"
"Number of address lines, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12"
(type "PARAMETER_UNSIGNED_DEC") )
(drawing
(line (pt 16 16)(pt 96 16))
(line (pt 16 80)(pt 96 80))
(line (pt 96 80)(pt 96 16))
(line (pt 16 80)(pt 16 16))
(rectangle (rect 16 16 144 96))
)
(annotation_block (parameter)(rect 872 -120 1202 13))
)
(connector
(text "1" (rect -94 -64 -89 -47)(font "Intel Clear" ))
@ -942,12 +917,6 @@ https://fpgasoftware.intel.com/eula.
(pt 1224 248)
(bus)
)
(connector
(text "0,0,0,0,0,0,0,0,EXTRA[7..0]" (rect 1144 232 1266 249)(font "Intel Clear" ))
(pt 1224 248)
(pt 1144 248)
(bus)
)
(connector
(text "A[0]" (rect 698 536 718 553)(font "Intel Clear" ))
(pt 720 552)
@ -972,12 +941,6 @@ https://fpgasoftware.intel.com/eula.
(pt 968 456)
(bus)
)
(connector
(text "B[7..0]" (rect 738 456 768 473)(font "Intel Clear" ))
(pt 728 472)
(pt 800 472)
(bus)
)
(connector
(text "0,0,0,0,0,0,0,0" (rect 730 424 793 441)(font "Intel Clear" ))
(pt 800 440)
@ -985,47 +948,85 @@ https://fpgasoftware.intel.com/eula.
(bus)
)
(connector
(text "<<__$DEF_ALIAS8980>>" (rect 96 392 214 409)(font "Intel Clear" )(invisible))
(pt 96 408)
(pt 192 408)
(text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
(pt 520 -16)
(pt 688 -16)
(bus)
)
(connector
(text "D[7..0]" (rect 354 392 384 409)(font "Intel Clear" ))
(pt 344 408)
(pt 392 408)
(pt 976 16)
(pt 976 152)
(bus)
)
(connector
(text "0,S[7..1]" (rect 578 -160 615 -143)(font "Intel Clear" ))
(pt 568 -136)
(pt 736 -136)
(pt 944 16)
(pt 976 16)
(bus)
)
(connector
(pt 944 -16)
(pt 992 -16)
(bus)
)
(connector
(pt 992 104)
(pt 992 -112)
(pt 992 -16)
(bus)
)
(connector
(pt 992 -112)
(pt 848 -112)
(text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
(pt 528 16)
(pt 688 16)
(bus)
)
(connector
(pt 976 152)
(pt 976 64)
(pt 688 48)
(pt 488 48)
)
(connector
(text "0,0,0,0,0,0,0,0,EXTRA[7..0]" (rect 1144 232 1266 249)(font "Intel Clear" ))
(pt 1224 248)
(pt 1144 248)
(bus)
)
(connector
(pt 976 64)
(pt 872 64)
(text "DIFF[7..0]" (rect 106 392 150 409)(font "Intel Clear" ))
(pt 96 408)
(pt 152 408)
(bus)
)
(connector
(text "0,D[7..1]" (rect 610 24 648 41)(font "Intel Clear" ))
(pt 600 40)
(pt 760 40)
(text "D[7..0]" (rect 474 232 504 249)(font "Intel Clear" ))
(pt 464 248)
(pt 512 248)
(bus)
)
(connector
(text "DIFF[7..0]" (rect 282 232 326 249)(font "Intel Clear" ))
(pt 312 248)
(pt 272 248)
(bus)
)
(connector
(pt 520 472)
(pt 800 472)
(bus)
)
(connector
(text "DIFF[7]" (rect 298 456 332 473)(font "Intel Clear" ))
(pt 360 472)
(pt 288 472)
)
(connector
(text "A[7..0]" (rect 298 472 328 489)(font "Intel Clear" ))
(pt 360 488)
(pt 288 488)
(bus)
)
(connector
(text "B[7..0]" (rect 298 488 328 505)(font "Intel Clear" ))
(pt 360 504)
(pt 288 504)
(bus)
)
(junction (pt -200 160))

17
mul8.bsf
View file

@ -27,17 +27,24 @@ https://fpgasoftware.intel.com/eula.
(port
(pt 0 32)
(input)
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 27 59 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)