Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog
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2020-05-29 09:47:44 -07:00
.gitignore Almost completed 16 bit multiplier. 2020-05-28 15:02:22 -07:00
abs.bdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
abs.bsf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
alu.v Initial ALU Verilog 2020-05-29 14:16:02 +01:00
CPUProject.bdf Revisions for testing 2020-05-27 18:53:59 +01:00
CPUProject.qpf Basic Project Setup 2020-05-20 12:44:57 +01:00
CPUProject.qsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
CPUProject.qws Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
CPUProject_assignment_defaults.qdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
data.mif Finished decoder 2020-05-27 18:53:03 +01:00
DECODE.bsf Finished decoder 2020-05-27 18:53:03 +01:00
DECODE.v Finished decoder 2020-05-27 18:53:03 +01:00
instr.mif Finished decoder 2020-05-27 18:53:03 +01:00
InstructionGenerator.cpp Added most of the code for generating the instruction MIF. Still need to do a big if-else statement for every instruction. 2020-05-28 14:42:02 -07:00
LUT.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUT.qip Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUT.v Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUTSquares.mif Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
min.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v.bak Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul8.bdf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul8.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul16.bdf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mux_8x16.bdf Working on initial design 2020-05-25 17:16:24 +01:00
mux_8x16.bsf Working on initial design 2020-05-25 17:16:24 +01:00
ram_data.bsf Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.qip Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.v Finished decoder 2020-05-27 18:53:03 +01:00
ram_instr.bsf Working on datapath 2020-05-27 11:10:13 +01:00
ram_instr.qip Working on datapath 2020-05-27 11:10:13 +01:00
ram_instr.v Finished decoder 2020-05-27 18:53:03 +01:00
README.md Initial commit 2020-05-20 12:05:19 +01:00
reg_file.bdf Finished datapath 2020-05-25 18:00:34 +01:00
reg_file.bsf Working on initial design 2020-05-25 17:16:24 +01:00
SM.bdf Working on datapath 2020-05-27 11:10:13 +01:00
SM.bsf Working on datapath 2020-05-27 11:10:13 +01:00
SquareMIFGenerator.cpp Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00

CPUProject