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supleed2/ ELEC40006-P1-CW

Verilog 0 0

Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog

verilog arm iverilog

Updated 2022-07-12 10:39:02 +00:00

supleed2/ ELEC50003-P1-CW

C 0 0

Yr2 Summer Term Rover Project, files for the various modules that make up an autonomous rover, designed to be similar to the 3D printer Pronterface UI

verilog autonomous-robots cpp platformio

Updated 2022-06-27 16:13:47 +00:00

supleed2/ ELEC50010-IAC-CW

Verilog 0 0

Synthesizable 32-bit MIPS 1 CPU, uses a memory-mapped bus to access memory and peripherals.

cpu fpga mips quartus-prime verilog

Updated 2020-12-21 21:16:28 +00:00