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• 561f8d88ce
  Update README.md master Kacper 2022-07-12 11:39:02 +0100
• 6ee15e92b3
  Uploaded demo to YT and changed link Kacper 2022-07-12 11:37:48 +0100
• 8d37df125f
  Fixed spelling mistake Kacper 2022-07-12 11:26:18 +0100
• 7f758952d3 Update reademe and add referenced files Aadi Desai 2022-06-27 15:51:35 +0000
• abb3e7979a Reorganise Repository Aadi Desai 2022-06-27 15:39:17 +0000
• 08dc6b9cec Merge remote-tracking branch 'origin/master-test' Aadi Desai 2022-06-27 15:36:05 +0000
• 0be656c893 Added old files from my desktop Kacper 2021-01-26 20:16:14 +0000
• 5dd725f7bf Brought up to date with Pipelined Kacper 2020-06-14 15:47:34 +0100
• 65ec0a4a41 Brought up to date with Pipelined Kacper 2020-06-14 15:38:43 +0100
• f169dd46e2 Almost up to date with Pipelined Kacper 2020-06-14 15:27:44 +0100
• 970fa6453e Finished Fibonacci testing Kacper 2020-06-13 02:43:38 +0100
• aff07036e0 Fixed multiplier bug Benjamin 2020-06-13 01:41:24 +0100
• aa2e7fd7fb Fixed the multiplier Benjamin 2020-06-13 01:29:56 +0100
• 3339ebd8a5 Forgot to apply edits to raw code ;( Kacper 2020-06-13 00:19:18 +0100
• e48831a92e Merge branch 'Add_CLL&RTN' of https://github.com/supleed2/CPUProject into Add_CLL&RTN Kacper 2020-06-13 00:05:00 +0100
• eacb943d5f Comment cleanup Kacper 2020-06-13 00:04:56 +0100
• 633ae2553b Finished testing CLL and RTN Kacper 2020-06-13 00:03:36 +0100
• f76a33c529 Merge branch 'Add_CLL&RTN' of https://github.com/supleed2/CPUProject into Add_CLL&RTN Kacper 2020-06-13 00:02:37 +0100
• be7b373cc2 Completed fibonacci testbench Kacper 2020-06-13 00:00:59 +0100
• 07b9ff4587 Added CLL and RTN Kacper 2020-06-12 22:12:43 +0100
• d7d55e74d4 Added testing for CLL and RTN Kacper 2020-06-12 22:12:04 +0100
• 4a29d1c83c Finished testing linked list Kacper 2020-06-12 21:37:25 +0100
• 9c1f71ac65 Fixed minor errors in list testbench Kacper 2020-06-12 18:41:35 +0100
• 0e8c242178 Some testing stuff Benjamin Ramhorst 2020-06-12 17:52:26 +0100
• bf747f2729 Testing linked list Kacper 2020-06-12 17:27:35 +0100
• 9a6e8b0837 Testing random generator Benjamin Ramhorst 2020-06-12 18:15:02 +0100
• e82aea9f44 Added test files Kacper 2020-06-12 17:05:51 +0100
• 64aa3329c4 Updated decoder to fully include JMA Kacper 2020-06-12 16:58:48 +0100
• d7fde1e905 Added JMA instruction and tested Kacper 2020-06-12 15:20:04 +0100
• c0ec656646 Added JMA instruction Kacper 2020-06-12 15:02:37 +0100
• f2ef3168a0 Update .gitignore Kacper 2020-06-12 12:44:18 +0100
• ce8367104c Update CPUProject.qws Kacper 2020-06-11 20:23:15 +0100
• e66c2af612 Removed RRC to optimise CPU Kacper 2020-06-11 17:57:54 +0100
• 87f3d0e919 CPU set up for testing and analysis Aadi Desai 2020-06-11 17:28:00 +0100
• 8496a6d42b Set up design for analysis Kacper 2020-06-11 17:27:49 +0100
• a9f0ec6d07 Create CPUProject.sdc Kacper 2020-06-11 16:45:15 +0100
• c14ac5e5de
  Merge pull request #2 from supleed2/master-test Aadi Desai 2020-06-11 16:24:19 +0100
• 6c1f7fc59b Remove debug lines from ALU to improve performance Aadi Desai 2020-06-11 16:23:16 +0100
• 4a01b182ec Update CPUProject.qws Kacper 2020-06-10 22:31:45 +0100
• d87d5c2f52 Create LIFO stack code.PNG Kacper 2020-06-10 22:17:42 +0100
• f4136c333b Create ALU Verilog snippet.PNG Kacper 2020-06-10 22:14:00 +0100
• b986060fea Pipelined CPU completed Kacper 2020-06-10 20:51:08 +0100
• d6bb9bd762 Added infrastructure for Fibonacci's number Benjamin Ramhorst 2020-06-10 20:10:34 +0100
• 3e4e5569b1 Added testing for Fibonacci and linked list Benjamin Ramhorst 2020-06-10 18:01:31 +0100
• 4688a56452 Modified Test Program to add LDR and STR Aadi Desai 2020-06-10 15:51:51 +0100
• 719c9ede2b Added decoder logic for STR and LDR Kacper 2020-06-10 14:40:58 +0100
• a1cf89e644 Added LDR and STR to alu and set up data paths Aadi Desai 2020-06-10 14:02:15 +0100
• a249245102 Merge branch 'master' of https://github.com/supleed2/CPUProject Kacper 2020-06-10 13:00:43 +0100
• 6839781fa0 Added STR and LDR to the cpp generator Kacper 2020-06-10 13:00:40 +0100
• d046242bc1 Final State before Pipelining Aadi Desai 2020-06-09 22:45:20 +0100
• 7a02c2c234
  Merge pull request #1 from supleed2/alu Aadi Desai 2020-06-09 20:35:41 +0100
• fefcad13ce Updated alu to feed only positive values to multiply block Aadi Desai 2020-06-09 20:34:29 +0100
• 12da9b94a5 Updated LUT to have an unregistered output Aadi Desai 2020-06-09 20:33:10 +0100
• 20f2adc4a1 Removed some waveform and test files Kacper 2020-06-09 19:01:55 +0100
• 46282576df Added pipelined SM and block needed for pipelining Kacper 2020-06-09 15:49:41 +0100
• 778dd7f538 Update test_no_mul.txt Kacper 2020-06-09 12:11:06 +0100
• 7b6806967d Update data.mif Kacper 2020-06-08 23:08:11 +0100
• 2f6cbeae56 Debugging complete! Kacper 2020-06-08 23:07:52 +0100
• c2ce212ed5 Fixed ASR in C++ generator Kacper 2020-06-08 21:37:12 +0100
• 47f20744ac Added new test mif with no multiplication Kacper 2020-06-08 13:13:26 +0100
• 24b293e24b Recompiled certain files Kacper 2020-06-08 12:10:14 +0100
• 8272afe500 Merge branch 'master' of https://github.com/supleed2/CPUProject Kacper 2020-06-07 23:23:20 +0100
• 3d9ea175cd Working on debugging Kacper 2020-06-07 23:23:13 +0100
• 64ca41b287 Resolved ISA conflict Kacper 2020-06-07 22:35:29 +0100
• b527d5e77d Debugging CPU Kacper 2020-06-07 20:51:33 +0100
• 94124c5a0e
  Update LIFOstack to support 32 memory slots Aadi Desai 2020-06-07 20:05:46 +0100
• 42739283f5 Update .gitignore Kacper 2020-06-07 17:45:40 +0100
• 24e22f13ec Fixed instrGen and added large test Kacper 2020-06-07 17:41:37 +0100
• 0b1ffea9ce Updated instruction generator to include new opcodes Kacper 2020-06-07 17:10:37 +0100
• 9a1a1da664 Complete CPU v2 (not tested) Kacper 2020-06-07 16:12:05 +0100
• 685f69a7cf Almost ready CPU Kacper 2020-06-07 15:08:34 +0100
• f6b3489884 Updated ALU to include PSH and POP Aadi Desai 2020-06-04 18:12:24 +0100
• 7997617e00 Add stack Verilog file Aadi Desai 2020-06-04 18:03:46 +0100
• 4318a5b70b CPU completed Kacper 2020-06-04 16:33:27 +0100
• 12bd671c00 Merge branch 'master' of https://github.com/supleed2/CPUProject Aadi Desai 2020-06-04 15:05:17 +0100
• 08a8635959 Updated ALU to use internal carry register Aadi Desai 2020-06-04 15:05:13 +0100
• f8edff65a1 Merge branch 'master' of https://github.com/supleed2/CPUProject Benjamin Ramhorst 2020-06-04 00:36:27 +0100
• 09dd851499 Completed source code for generating .mif files from opcodes and registers Benjamin Ramhorst 2020-06-04 00:36:11 +0100
• 3647e0b15c ALU now uses multiply block rather than * operator Aadi Desai 2020-06-03 15:15:44 +0100
• 1c0032fa95 Fixed decoder and SM Kacper 2020-06-02 20:09:22 +0100
• e1d7bf884d Merge branch 'master' of https://github.com/supleed2/CPUProject Aadi Desai 2020-06-02 16:58:04 +0100
• 2ca1e90a2c ALU enable control added, minor fix with RRC Aadi Desai 2020-06-02 16:57:58 +0100
• 5d6c9803fc Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available ben 2020-05-29 09:47:44 -0700
• 3f0c91b0ff
  Initial ALU Verilog Aadi Desai 2020-05-29 14:16:02 +0100
• fedfcaaada
  Added most of the code for generating the instruction MIF. Still need to do a big if-else statement for every instruction. Benjamin Ramhorst 2020-05-28 14:42:02 -0700
• 3d6e456fcc Almost completed 16 bit multiplier. ben 2020-05-28 15:02:22 -0700
• e39d2f653a Started working on the multiply block. Added absolute value block. ben 2020-05-28 09:11:14 -0700
• 132e1ad7fe
  Delete DECODE.v.bak Kacper 2020-05-27 18:59:12 +0100
• cf179ad2cf Revisions for testing Kacper 2020-05-27 18:53:59 +0100
• e1acb56b66 Finished decoder Kacper 2020-05-27 18:53:03 +0100
• 1747e0c0b2 Delete cbx_args.txt Kacper 2020-05-27 11:10:59 +0100
• 5ed70dabb0 Working on datapath Kacper 2020-05-27 11:10:13 +0100
• 9db1fb0af6 Added the look-up table and the code used to generate it Benjamin Ramhorst 2020-05-25 22:47:29 +0100
• 3b298e02a2 Finished datapath Kacper 2020-05-25 18:00:34 +0100
• 6b2363d6a1 Working on initial design Kacper 2020-05-25 17:16:24 +0100
• 14418c8725 VCS Test Benjamin 2020-05-20 19:24:20 +0100
• 26c28a829d Basic Project Setup Aadi Desai 2020-05-20 12:44:57 +0100
• 29cb9493a1
  Add gitignore for quartus Aadi Desai 2020-05-20 12:08:03 +0100
• d86f15262c
  Initial commit Aadi Desai 2020-05-20 12:05:19 +0100