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Kacper
parent
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commit
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11
ALU_top.bdf
11
ALU_top.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
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@ -299,8 +298,8 @@ https://fpgasoftware.intel.com/eula.
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the Block Editor! File corruption is VERY likely to occur.
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*/
|
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/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
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223
CPUProject.bdf
223
CPUProject.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
|
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*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
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@ -990,7 +890,7 @@ https://fpgasoftware.intel.com/eula.
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(pt 112 48)
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|
@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
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||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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@ -62,12 +62,13 @@ set_global_assignment -name POWER_USE_PVA ON
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|||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE max_min.v
|
||||
set_global_assignment -name SDC_FILE CPUProject.sdc
|
||||
set_global_assignment -name VERILOG_FILE LIFOstack.v
|
||||
set_global_assignment -name VERILOG_FILE alu.v
|
||||
set_global_assignment -name MIF_FILE LUTSquares.mif
|
||||
set_global_assignment -name BDF_FILE mul8.bdf
|
||||
set_global_assignment -name BDF_FILE abs.bdf
|
||||
set_global_assignment -name BDF_FILE CPUProject.bdf
|
||||
set_global_assignment -name BDF_FILE reg_file.bdf
|
||||
set_global_assignment -name QIP_FILE ram_data.qip
|
||||
|
|
@ -77,13 +78,8 @@ set_global_assignment -name MIF_FILE data.mif
|
|||
set_global_assignment -name MIF_FILE instr.mif
|
||||
set_global_assignment -name BDF_FILE mul16.bdf
|
||||
set_global_assignment -name QIP_FILE LUT.qip
|
||||
set_global_assignment -name VERILOG_FILE min.v
|
||||
set_global_assignment -name VERILOG_FILE SM.v
|
||||
set_global_assignment -name BDF_FILE ALU_top.bdf
|
||||
set_global_assignment -name VERILOG_FILE mux_8x16.v
|
||||
set_global_assignment -name VERILOG_FILE mux_3x16.v
|
||||
set_global_assignment -name VERILOG_FILE ADD_1.v
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
BIN
CPUProject.qws
BIN
CPUProject.qws
Binary file not shown.
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
|
|
|
|||
48
DECODE.v
48
DECODE.v
|
|
@ -41,7 +41,8 @@ module DECODE
|
|||
//Different opcodes (refer to documentation):
|
||||
wire LDA = msb & ~ls;
|
||||
wire STA = msb & ls;
|
||||
wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
|
||||
wire JMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
|
||||
wire JMA = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
|
||||
wire JCX = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
|
||||
wire MUL = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
|
||||
wire MLA = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
|
||||
|
|
@ -50,37 +51,38 @@ module DECODE
|
|||
wire POP = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
|
||||
wire LDR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0];
|
||||
wire STR = ~msb & op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
|
||||
wire CLL = ~msb & op[5] & ~op[4] & ~op[3] & op[2] & op[1] & ~op[0];
|
||||
wire RTN = ~msb & op[5] & ~op[4] & ~op[3] & op[2] & op[1] & op[0];
|
||||
wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
|
||||
wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
|
||||
|
||||
assign R0_count = EXEC1 & (~(JMP | (JCX & COND_result) | STP));
|
||||
assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | JCX & COND_result)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
|
||||
assign R1_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]);
|
||||
assign R2_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]);
|
||||
assign R3_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & Rd[1] & Rd[0]);
|
||||
assign R4_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]);
|
||||
assign R5_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & ~Rd[1] & Rd[0]);
|
||||
assign R6_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & ~Rd[0]);
|
||||
assign R7_en = (EXEC1 & ~(JMP | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & Rd[2] & Rd[1] & Rd[0]);
|
||||
assign s1[2] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[2]) | (STA & Rls[2]);
|
||||
assign s1[1] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[1]) | (STA & Rls[1]);
|
||||
assign s1[0] = (~(JMP | STA | LDA | NOP | STP | POP) & Rs1[0]) | (STA & Rls[0]);
|
||||
assign s2[2] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[2]);
|
||||
assign s2[1] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[1]);
|
||||
assign s2[0] = (~(JMP | STA | LDA | NOP | STP | POP | PSH | LDR | STR) & Rs2[0]);
|
||||
assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[2]);
|
||||
assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[1]);
|
||||
assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP) & Rd[0]);
|
||||
assign R0_count = EXEC1 & (~(JMP | JMA | (JCX & COND_result) | STP | CLL | RTN));
|
||||
assign R0_en = (EXEC1 & (~(STA | NOP | STP | LDA | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] & ~Rd[0] | JMP | (JCX & COND_result) | JMA)) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | STR | LDR) & ~Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & RTN) | (EXEC1 & CLL);
|
||||
assign R1_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & ~Rd[1] & Rd[0]);
|
||||
assign R2_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & Rd[1] & ~Rd[0]);
|
||||
assign R3_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & ~Rd[2] & Rd[1] & Rd[0]);
|
||||
assign R4_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & ~Rd[1] & ~Rd[0]);
|
||||
assign R5_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & ~Rd[1] & Rd[0]);
|
||||
assign R6_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & Rd[1] & ~Rd[0]);
|
||||
assign R7_en = (EXEC1 & ~(JMP | JMA | JCX | STA | LDA | MUL | MLA | MLS | NOP | STP | POP | PSH | LDR | CLL | RTN) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LDA & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP | LDR) & Rd[2] & Rd[1] & Rd[0]);
|
||||
assign s1[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[2]) | (STA & Rls[2]);
|
||||
assign s1[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[1]) | (STA & Rls[1]);
|
||||
assign s1[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | CLL | RTN) & Rs1[0]) | (STA & Rls[0]);
|
||||
assign s2[2] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[2]);
|
||||
assign s2[1] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[1]);
|
||||
assign s2[0] = (~(JMP | JMA | STA | LDA | NOP | STP | POP | PSH | LDR | STR | CLL | RTN) & Rs2[0]);
|
||||
assign s3[2] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[2]);
|
||||
assign s3[1] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[1]);
|
||||
assign s3[0] = (~(STA | LDA | NOP | STP | PSH | POP | RTN) & Rd[0]);
|
||||
assign s4 = ~(LDA | LDR);
|
||||
assign RAMd_wren = EXEC1 & (STA | STR);
|
||||
assign RAMd_en = EXEC1 & (STA | LDA | STR | LDR);
|
||||
assign RAMi_en = FETCH;
|
||||
assign ALU_en = LDA | STA;
|
||||
assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR);
|
||||
assign stack_en = (EXEC1 & PSH) | ((EXEC1 | EXEC2) & POP);
|
||||
assign E2 = EXEC1 & (LDA | MUL | MLA | MLS | POP | LDR | RTN);
|
||||
assign stack_en = (EXEC1 & (PSH | CLL | RTN | POP));
|
||||
assign stack_rst = STP;
|
||||
assign stack_rw = EXEC1 & PSH;
|
||||
assign stack_rw = EXEC1 & (PSH | CLL);
|
||||
assign s5 = EXEC1 & (STR | LDR);
|
||||
|
||||
endmodule
|
||||
|
||||
11
alu.bsf
11
alu.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
|
|
@ -55,8 +54,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "opcode[5..0]" (rect 0 0 48 12)(font "Arial" ))
|
||||
(text "opcode[5..0]" (rect 21 91 69 103)(font "Arial" ))
|
||||
(text "instr[15..0]" (rect 0 0 40 12)(font "Arial" ))
|
||||
(text "instr[15..0]" (rect 21 91 61 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
|
|
|
|||
19
alu.v
19
alu.v
|
|
@ -1,10 +1,10 @@
|
|||
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
|
||||
module alu (enable, Rs1, Rs2, Rd, instr, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
|
||||
|
||||
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
|
||||
input signed [15:0] Rs1; // input source register 1
|
||||
input signed [15:0] Rs2; // input source register 2
|
||||
input signed [15:0] Rd; // input destination register
|
||||
input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
|
||||
input [15:0] instr; // opcode is fed in from instruction using wires outside ALU
|
||||
input signed [31:0] mulresult; // 32-bit result from multiplier
|
||||
input exec2; // Input from state machine to indicate when to take in result from multiplication
|
||||
input [15:0] stackout; // input from stack to be fed back to registers
|
||||
|
|
@ -13,9 +13,10 @@ output reg signed [15:0] mul1; // first number to be multiplied
|
|||
output reg signed [15:0] mul2; // second number to be multiplied
|
||||
output signed [15:0] Rout; // value to be saved to destination register
|
||||
output jump; // tells decoder whether Jump condition is true
|
||||
reg carry; // Internal carry register that is updated during appropriate opcodes
|
||||
reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
|
||||
output reg [10:0] memaddr; // address to load data from / store data to RAMd
|
||||
|
||||
wire [5:0]opcode = instr[14:9]; //opcode of current instruction
|
||||
reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
|
||||
assign Rout = alusum [15:0];
|
||||
assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010)));
|
||||
|
|
@ -157,9 +158,13 @@ always @(opcode, mulresult)
|
|||
6'b100011: ;
|
||||
|
||||
6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
|
||||
6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
|
||||
6'b100110: ;
|
||||
6'b100111: ;
|
||||
// 6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
|
||||
6'b100110: alusum = {1'b1, Rd}; //CLL function call
|
||||
6'b100111: begin //RTN return to prev call
|
||||
if(exec2) begin
|
||||
alusum = {1'b0, stackout};
|
||||
end
|
||||
end
|
||||
|
||||
6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1)
|
||||
6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack)
|
||||
|
|
@ -183,4 +188,4 @@ always @(opcode, mulresult)
|
|||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
64
mux_3x16.bsf
64
mux_3x16.bsf
|
|
@ -1,64 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 200 128)
|
||||
(text "mux_3x16" (rect 5 0 46 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 20 108)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "s[1..0]" (rect 0 0 23 12)(font "Arial" ))
|
||||
(text "s[1..0]" (rect 21 27 44 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "in0[15..0]" (rect 0 0 34 12)(font "Arial" ))
|
||||
(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
|
||||
(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "in2[15..0]" (rect 0 0 34 12)(font "Arial" ))
|
||||
(text "in2[15..0]" (rect 21 75 55 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
|
||||
(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 96)(line_width 1))
|
||||
)
|
||||
)
|
||||
19
mux_3x16.v
19
mux_3x16.v
|
|
@ -1,19 +0,0 @@
|
|||
module mux_3x16 (s, in0, in1, in2, result);
|
||||
|
||||
input [1:0]s;
|
||||
input [15:0]in0;
|
||||
input [15:0]in1;
|
||||
input [15:0]in2;
|
||||
|
||||
output reg [15:0]result;
|
||||
|
||||
always @(*) begin
|
||||
case(s)
|
||||
2'b00: result = in0;
|
||||
2'b01: result = in1;
|
||||
2'b10: result = in2;
|
||||
default: result = in0;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
module mux_3x16 (s, in0, in1, in2, result);
|
||||
|
||||
input [1:0]s;
|
||||
input [15:0]in0;
|
||||
input [15:0]in1;
|
||||
input [15:0]in2;
|
||||
|
||||
output reg [15:0]result;
|
||||
|
||||
always @(*) begin
|
||||
case(s)
|
||||
2'b00: result = in0;
|
||||
2'b01: result = in1;
|
||||
2'b10: result = in2;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in a new issue