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Remove debug lines from ALU to improve performance
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10
alu.v
10
alu.v
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@ -1,4 +1,4 @@
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module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr);
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module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, memaddr);
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input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
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input signed [15:0] Rs1; // input source register 1
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@ -8,14 +8,12 @@ input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
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input signed [31:0] mulresult; // 32-bit result from multiplier
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input exec2; // Input from state machine to indicate when to take in result from multiplication
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input [15:0] stackout; // input from stack to be fed back to registers
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input signed [15:0] memdatain; // input data from RAMd
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output reg signed [15:0] mul1; // first number to be multiplied
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output reg signed [15:0] mul2; // second number to be multiplied
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output signed [15:0] Rout; // value to be saved to destination register
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output jump; // tells decoder whether Jump condition is true
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output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
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output [7:0] jumpflags;
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reg carry; // Internal carry register that is updated during appropriate opcodes
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output reg [10:0] memaddr; // address to load data from / store data to RAMd
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reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
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@ -33,7 +31,6 @@ assign JC5 = (Rs1 >= Rs2);
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assign JC6 = (Rs1 <= Rs2);
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assign JC7 = (Rs1 != Rs2);
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assign JC8 = (Rs1 < 0);
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assign jumpflags = {JC1, JC2, JC3, JC4, JC5, JC6, JC7, JC8};
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always @(opcode, mulresult)
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begin
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@ -170,9 +167,6 @@ always @(opcode, mulresult)
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if(!exec2) begin
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memaddr = Rs1[10:0];
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end
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else begin
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alusum = {1'b0, memdatain};
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end
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end
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6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
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memaddr = Rd[10:0];
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