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synced 2024-09-19 20:26:18 +00:00
Brought up to date with Pipelined
This commit is contained in:
Kacper
parent
f169dd46e2
commit
65ec0a4a41
|
|
@ -263,7 +263,7 @@ refer to the applicable agreement for further details.
|
|||
(output)
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(rect 800 336 976 352)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(text "memaddr[10..0]" (rect 90 0 165 17)(font "Intel Clear" ))
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18
ALU_top.bsf
18
ALU_top.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
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|||
the Block Editor! File corruption is VERY likely to occur.
|
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*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
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@ -76,16 +75,9 @@ https://fpgasoftware.intel.com/eula.
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*/
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/*
|
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Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
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*/
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(header "graphic" (version "1.4"))
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@ -1465,16 +1464,9 @@ https://fpgasoftware.intel.com/eula.
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|
|
@ -62,11 +62,12 @@ set_global_assignment -name POWER_USE_PVA ON
|
|||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VERILOG_FILE max_min.v
|
||||
set_global_assignment -name VERILOG_FILE LIFOstack.v
|
||||
set_global_assignment -name VERILOG_FILE alu.v
|
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set_global_assignment -name MIF_FILE LUTSquares.mif
|
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set_global_assignment -name BDF_FILE mul8.bdf
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||||
set_global_assignment -name BDF_FILE abs.bdf
|
||||
set_global_assignment -name BDF_FILE CPUProject.bdf
|
||||
set_global_assignment -name BDF_FILE reg_file.bdf
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||||
set_global_assignment -name QIP_FILE ram_data.qip
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|
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@ -76,12 +77,8 @@ set_global_assignment -name MIF_FILE data.mif
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set_global_assignment -name MIF_FILE instr.mif
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set_global_assignment -name BDF_FILE mul16.bdf
|
||||
set_global_assignment -name QIP_FILE LUT.qip
|
||||
set_global_assignment -name VERILOG_FILE min.v
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||||
set_global_assignment -name VERILOG_FILE SM.v
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||||
set_global_assignment -name BDF_FILE ALU_top.bdf
|
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set_global_assignment -name VERILOG_FILE mux_8x16.v
|
||||
set_global_assignment -name VERILOG_FILE mux_3x16.v
|
||||
set_global_assignment -name VERILOG_FILE ADD_1.v
|
||||
set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
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set_global_assignment -name VERILOG_FILE SM_pipelined.v
|
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BIN
CPUProject.qws
Normal file
BIN
CPUProject.qws
Normal file
Binary file not shown.
769
abs.bdf
769
abs.bdf
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@ -1,769 +0,0 @@
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
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|
||||
to the terms and conditions of the Intel Program License
|
||||
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|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
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||||
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(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 11 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 11 32))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 49 24)(pt 64 24))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 13)(pt 25 13))
|
||||
(line (pt 14 36)(pt 25 36))
|
||||
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
|
||||
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
|
||||
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
|
||||
(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 408 480 472 528)
|
||||
(text "XOR" (rect 1 0 21 10)(font "Arial" (font_size 6)))
|
||||
(text "C7" (rect 3 37 15 54)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 11 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 11 32))
|
||||
)
|
||||
(port
|
||||
(pt 64 24)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 49 24)(pt 64 24))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 14 13)(pt 25 13))
|
||||
(line (pt 14 36)(pt 25 36))
|
||||
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
|
||||
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
|
||||
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
|
||||
(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 120 288 152 304)
|
||||
(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
|
||||
(text "inst" (rect 3 5 20 17)(font "Arial" )(invisible))
|
||||
(port
|
||||
(pt 16 16)
|
||||
(output)
|
||||
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
|
||||
(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 16 16)(pt 16 8))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 8 8)(pt 24 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 168 280 200 312)
|
||||
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
|
||||
(text "inst5" (rect 3 21 25 38)(font "Intel Clear" )(invisible))
|
||||
(port
|
||||
(pt 16 0)
|
||||
(output)
|
||||
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
|
||||
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 16 8)(pt 16 0))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 8 8)(pt 16 16))
|
||||
(line (pt 16 16)(pt 24 8))
|
||||
(line (pt 8 8)(pt 24 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 968 136 1128 304)
|
||||
(text "LPM_ADD_SUB" (rect 37 0 149 16)(font "Arial" (font_size 10)))
|
||||
(text "FA_ABS" (rect 3 156 41 173)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 130 41 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 15 144))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
|
||||
(text "add_sub" (rect 20 17 69 31)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 15 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "cin" (rect 20 34 36 48)(font "Arial" (font_size 8)))
|
||||
(text "cin" (rect 20 34 36 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 15 48))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(text "clken" (rect 20 90 49 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 56 104))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 88)
|
||||
(input)
|
||||
(text "clock" (rect 20 74 49 88)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 20 74 49 88)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 88)(pt 56 88))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "dataa[LPM_WIDTH-1..0]" (rect 20 57 153 71)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 20 57 58 71)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 15 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "datab[LPM_WIDTH-1..0]" (rect 20 105 153 119)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 20 105 58 119)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 15 120)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 144)
|
||||
(output)
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(text "cout" (rect 120 129 144 143)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 144)(pt 160 144))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 160 128)
|
||||
(output)
|
||||
(text "overflow" (rect 99 113 150 127)(font "Arial" (font_size 8)))
|
||||
(text "overflow" (rect 97 113 148 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 128)(pt 160 128))
|
||||
(unused)
|
||||
)
|
||||
(port
|
||||
(pt 160 96)
|
||||
(output)
|
||||
(text "result[LPM_WIDTH-1..0]" (rect 109 81 242 95)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 108 81 146 95)(font "Arial" (font_size 8)))
|
||||
(line (pt 145 96)(pt 160 96)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"LPM_WIDTH"
|
||||
"8"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
(type "PARAMETER_UNSIGNED_DEC") )
|
||||
(drawing
|
||||
(line (pt 16 48)(pt 72 48))
|
||||
(line (pt 16 152)(pt 144 152))
|
||||
(line (pt 16 16)(pt 144 16))
|
||||
(line (pt 16 72)(pt 56 72)(line_width 3))
|
||||
(line (pt 16 120)(pt 56 120)(line_width 3))
|
||||
(line (pt 104 96)(pt 144 96)(line_width 3))
|
||||
(line (pt 88 128)(pt 144 128))
|
||||
(line (pt 16 32)(pt 88 32))
|
||||
(line (pt 80 144)(pt 144 144))
|
||||
(line (pt 16 144)(pt 72 144))
|
||||
(line (pt 104 112)(pt 104 80))
|
||||
(line (pt 88 128)(pt 88 120))
|
||||
(line (pt 16 152)(pt 16 16))
|
||||
(line (pt 144 152)(pt 144 16))
|
||||
(line (pt 56 136)(pt 56 56))
|
||||
(line (pt 72 64)(pt 72 48))
|
||||
(line (pt 88 72)(pt 88 32))
|
||||
(line (pt 80 144)(pt 80 124))
|
||||
(line (pt 72 144)(pt 72 128))
|
||||
(line (pt 56 56)(pt 104 80))
|
||||
(line (pt 56 136)(pt 104 112))
|
||||
)
|
||||
(annotation_block (parameter)(rect 960 96 1154 134))
|
||||
)
|
||||
(symbol
|
||||
(rect 784 120 896 208)
|
||||
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
|
||||
(text "ADD1" (rect 3 77 36 91)(font "Arial" (font_size 8)))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
|
||||
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 44 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 56 88)
|
||||
(input)
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
|
||||
(line (pt 56 88)(pt 56 72))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
|
||||
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 44 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 112 48)
|
||||
(output)
|
||||
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
|
||||
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
|
||||
(line (pt 68 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"WIDTH"
|
||||
"8"
|
||||
"Width of I/O, any integer > 0"
|
||||
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
|
||||
(type "PARAMETER_UNSIGNED_DEC") )
|
||||
(drawing
|
||||
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
|
||||
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
|
||||
(line (pt 68 64)(pt 68 32))
|
||||
(line (pt 44 80)(pt 44 16))
|
||||
(line (pt 44 16)(pt 68 32))
|
||||
(line (pt 44 80)(pt 68 64))
|
||||
)
|
||||
(annotation_block (parameter)(rect 720 80 902 118))
|
||||
)
|
||||
(connector
|
||||
(pt 232 176)
|
||||
(pt 312 176)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "N[0]" (rect 362 32 382 49)(font "Intel Clear" ))
|
||||
(pt 384 48)
|
||||
(pt 408 48)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 362 56 382 73)(font "Intel Clear" ))
|
||||
(pt 384 64)
|
||||
(pt 408 64)
|
||||
)
|
||||
(connector
|
||||
(text "N[1]" (rect 368 96 388 113)(font "Intel Clear" ))
|
||||
(pt 390 112)
|
||||
(pt 408 112)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 112 388 129)(font "Intel Clear" ))
|
||||
(pt 390 128)
|
||||
(pt 408 128)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 176 388 193)(font "Intel Clear" ))
|
||||
(pt 390 192)
|
||||
(pt 408 192)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 240 388 257)(font "Intel Clear" ))
|
||||
(pt 390 256)
|
||||
(pt 408 256)
|
||||
)
|
||||
(connector
|
||||
(text "N[2]" (rect 368 160 388 177)(font "Intel Clear" ))
|
||||
(pt 390 176)
|
||||
(pt 408 176)
|
||||
)
|
||||
(connector
|
||||
(text "N[3]" (rect 368 224 388 241)(font "Intel Clear" ))
|
||||
(pt 390 240)
|
||||
(pt 408 240)
|
||||
)
|
||||
(connector
|
||||
(text "N[4]" (rect 368 288 388 305)(font "Intel Clear" ))
|
||||
(pt 390 304)
|
||||
(pt 408 304)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 304 388 321)(font "Intel Clear" ))
|
||||
(pt 390 320)
|
||||
(pt 408 320)
|
||||
)
|
||||
(connector
|
||||
(text "N[5]" (rect 368 352 388 369)(font "Intel Clear" ))
|
||||
(pt 390 368)
|
||||
(pt 408 368)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 368 388 385)(font "Intel Clear" ))
|
||||
(pt 390 384)
|
||||
(pt 408 384)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 432 388 449)(font "Intel Clear" ))
|
||||
(pt 390 448)
|
||||
(pt 408 448)
|
||||
)
|
||||
(connector
|
||||
(text "N[6]" (rect 368 416 388 433)(font "Intel Clear" ))
|
||||
(pt 390 432)
|
||||
(pt 408 432)
|
||||
)
|
||||
(connector
|
||||
(pt 512 24)
|
||||
(pt 512 56)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 56)
|
||||
(pt 512 120)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 120)
|
||||
(pt 512 184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 184)
|
||||
(pt 512 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 312)
|
||||
(pt 512 376)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "T[0]" (rect 482 40 500 57)(font "Intel Clear" ))
|
||||
(pt 472 56)
|
||||
(pt 512 56)
|
||||
)
|
||||
(connector
|
||||
(text "T[1]" (rect 482 104 500 121)(font "Intel Clear" ))
|
||||
(pt 472 120)
|
||||
(pt 512 120)
|
||||
)
|
||||
(connector
|
||||
(text "T[2]" (rect 482 168 500 185)(font "Intel Clear" ))
|
||||
(pt 472 184)
|
||||
(pt 512 184)
|
||||
)
|
||||
(connector
|
||||
(text "T[3]" (rect 482 232 500 249)(font "Intel Clear" ))
|
||||
(pt 472 248)
|
||||
(pt 512 248)
|
||||
)
|
||||
(connector
|
||||
(text "T[4]" (rect 482 296 500 313)(font "Intel Clear" ))
|
||||
(pt 472 312)
|
||||
(pt 512 312)
|
||||
)
|
||||
(connector
|
||||
(text "T[5]" (rect 482 360 500 377)(font "Intel Clear" ))
|
||||
(pt 472 376)
|
||||
(pt 512 376)
|
||||
)
|
||||
(connector
|
||||
(text "T[6]" (rect 482 424 500 441)(font "Intel Clear" ))
|
||||
(pt 472 440)
|
||||
(pt 512 440)
|
||||
)
|
||||
(connector
|
||||
(pt 512 376)
|
||||
(pt 512 440)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 496 388 513)(font "Intel Clear" ))
|
||||
(pt 390 512)
|
||||
(pt 408 512)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 368 480 388 497)(font "Intel Clear" ))
|
||||
(pt 390 496)
|
||||
(pt 408 496)
|
||||
)
|
||||
(connector
|
||||
(pt 512 440)
|
||||
(pt 512 504)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 504)
|
||||
(pt 512 520)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "T[7]" (rect 482 488 500 505)(font "Intel Clear" ))
|
||||
(pt 472 504)
|
||||
(pt 512 504)
|
||||
)
|
||||
(connector
|
||||
(pt 1128 232)
|
||||
(pt 1152 232)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "1" (rect 120 315 137 320)(font "Intel Clear" )(vertical))
|
||||
(pt 136 304)
|
||||
(pt 136 320)
|
||||
)
|
||||
(connector
|
||||
(text "0" (rect 168 273 185 278)(font "Intel Clear" )(vertical))
|
||||
(pt 184 256)
|
||||
(pt 184 280)
|
||||
)
|
||||
(connector
|
||||
(text "N[7]" (rect 824 205 841 225)(font "Intel Clear" )(vertical))
|
||||
(pt 840 208)
|
||||
(pt 840 232)
|
||||
)
|
||||
(connector
|
||||
(text "0,0,0,0,0,0,0,0" (rect 682 136 745 153)(font "Intel Clear" ))
|
||||
(pt 784 152)
|
||||
(pt 672 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "0,0,0,0,0,0,0,1" (rect 682 168 745 185)(font "Intel Clear" ))
|
||||
(pt 672 184)
|
||||
(pt 784 184)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 896 168)
|
||||
(pt 912 168)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 912 168)
|
||||
(pt 912 208)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 912 208)
|
||||
(pt 968 208)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "T[7..0]" (rect 522 256 551 273)(font "Intel Clear" ))
|
||||
(pt 856 272)
|
||||
(pt 512 272)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 272)
|
||||
(pt 856 256)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 248)
|
||||
(pt 512 272)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 512 272)
|
||||
(pt 512 312)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 856 256)
|
||||
(pt 968 256)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "1" (rect 954 152 959 169)(font "Intel Clear" ))
|
||||
(pt 968 168)
|
||||
(pt 944 168)
|
||||
)
|
||||
(junction (pt 512 56))
|
||||
(junction (pt 512 120))
|
||||
(junction (pt 512 184))
|
||||
(junction (pt 512 248))
|
||||
(junction (pt 512 312))
|
||||
(junction (pt 512 376))
|
||||
(junction (pt 512 440))
|
||||
(junction (pt 512 272))
|
||||
(junction (pt 512 504))
|
||||
44
abs.bsf
44
abs.bsf
|
|
@ -1,44 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 168 112)
|
||||
(text "abs" (rect 5 0 26 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "N[7..0]" (rect 0 0 40 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "N[7..0]" (rect 21 27 61 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 152 32)
|
||||
(output)
|
||||
(text "ABS[7..0]" (rect 0 0 55 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "ABS[7..0]" (rect 76 27 131 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 152 32)(pt 136 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 136 80))
|
||||
)
|
||||
)
|
||||
|
|
@ -20,45 +20,38 @@ refer to the applicable agreement for further details.
|
|||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 200 128)
|
||||
(text "mux_3x16" (rect 5 0 46 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 20 108)(font "Arial" ))
|
||||
(rect 16 16 200 96)
|
||||
(text "max_min" (rect 5 0 42 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 64 20 76)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "s[1..0]" (rect 0 0 23 12)(font "Arial" ))
|
||||
(text "s[1..0]" (rect 21 27 44 39)(font "Arial" ))
|
||||
(text "a[7..0]" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "a[7..0]" (rect 21 27 45 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "in0[15..0]" (rect 0 0 34 12)(font "Arial" ))
|
||||
(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
|
||||
(text "b[7..0]" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "b[7..0]" (rect 21 43 45 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
|
||||
(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "in2[15..0]" (rect 0 0 34 12)(font "Arial" ))
|
||||
(text "in2[15..0]" (rect 21 75 55 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
|
||||
(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
|
||||
(text "maximum[7..0]" (rect 0 0 60 12)(font "Arial" ))
|
||||
(text "maximum[7..0]" (rect 103 27 163 39)(font "Arial" ))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(output)
|
||||
(text "minimum[7..0]" (rect 0 0 56 12)(font "Arial" ))
|
||||
(text "minimum[7..0]" (rect 107 43 163 55)(font "Arial" ))
|
||||
(line (pt 184 48)(pt 168 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 96)(line_width 1))
|
||||
(rectangle (rect 16 16 168 64)(line_width 1))
|
||||
)
|
||||
)
|
||||
11
max_min.v
Normal file
11
max_min.v
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
module max_min(a, b, maximum, minimum);
|
||||
|
||||
input unsigned [7:0] a;
|
||||
input unsigned [7:0] b;
|
||||
output unsigned [7:0] maximum;
|
||||
output unsigned [7:0] minimum;
|
||||
|
||||
assign minimum = (a<b) ? a:b;
|
||||
assign maximum = (a>b) ? a:b;
|
||||
|
||||
endmodule
|
||||
11
max_min.v.bak
Normal file
11
max_min.v.bak
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
module min_max(a, b, minimum, maximum);
|
||||
|
||||
input unsigned [7..0] a;
|
||||
input unsigned [7..0] b;
|
||||
output unsigned [7..0] minimum;
|
||||
output unsigned [7..0] maximum;
|
||||
|
||||
assign minimum = (a<b) ? a:b;
|
||||
assign maximum = (a>b) ? a:b;
|
||||
|
||||
endmodule
|
||||
58
min.bsf
58
min.bsf
|
|
@ -1,58 +0,0 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 176 128)
|
||||
(text "min" (rect 5 0 19 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 20 108)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "sign" (rect 0 0 15 12)(font "Arial" ))
|
||||
(text "sign" (rect 21 27 36 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "a[7..0]" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "a[7..0]" (rect 21 43 45 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "b[7..0]" (rect 0 0 24 12)(font "Arial" ))
|
||||
(text "b[7..0]" (rect 21 59 45 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 32)
|
||||
(output)
|
||||
(text "num[7..0]" (rect 0 0 37 12)(font "Arial" ))
|
||||
(text "num[7..0]" (rect 102 27 139 39)(font "Arial" ))
|
||||
(line (pt 160 32)(pt 144 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 144 96)(line_width 1))
|
||||
)
|
||||
)
|
||||
7
min.v
7
min.v
|
|
@ -1,7 +0,0 @@
|
|||
module min(sign, a, b, num);
|
||||
input sign;
|
||||
input [7:0] a;
|
||||
input [7:0] b;
|
||||
output [7:0] num;
|
||||
assign num = sign ? a[7:0]:b[7:0];
|
||||
endmodule
|
||||
12
min.v.bak
12
min.v.bak
|
|
@ -1,12 +0,0 @@
|
|||
module MIN(
|
||||
input sign,
|
||||
input a[7..0],
|
||||
input b[7..0],
|
||||
output [7..0] num;
|
||||
);
|
||||
|
||||
assign num = sign ? a[7..0]:b[7..0]
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
351
mul16.bdf
351
mul16.bdf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
|
|
@ -507,150 +506,6 @@ https://fpgasoftware.intel.com/eula.
|
|||
)
|
||||
(annotation_block (parameter)(rect 1728 48 2038 181))
|
||||
)
|
||||
(symbol
|
||||
(rect 648 56 816 152)
|
||||
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL1" (rect 8 75 36 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 648 176 816 272)
|
||||
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL2" (rect 8 75 36 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
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|
||||
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 648 288 816 384)
|
||||
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL3" (rect 8 75 36 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 648 392 816 488)
|
||||
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "MUL4" (rect 8 75 36 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "CLOCK" (rect 0 0 41 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "CLOCK" (rect 21 27 62 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 168 160 200 192)
|
||||
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
|
||||
|
|
@ -668,6 +523,150 @@ https://fpgasoftware.intel.com/eula.
|
|||
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
|
||||
|
|
@ -16,8 +16,7 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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refer to the applicable agreement for further details.
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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||||
and other software and tools, and any partner logic
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||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
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||||
(including device programming or simulation files), and any
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||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,42 +16,9 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 32)
|
||||
(output)
|
||||
(text "maximum[7..0]" (rect 0 0 74 12)(font "Arial" ))
|
||||
(text "maximum[7..0]" (rect 101 27 163 39)(font "Arial" ))
|
||||
(line (pt 184 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 184 48)
|
||||
(output)
|
||||
(text "minimum[7..0]" (rect 0 0 70 12)(font "Arial" ))
|
||||
(text "minimum[7..0]" (rect 104 43 163 55)(font "Arial" ))
|
||||
(line (pt 184 48)(pt 168 48)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 168 64))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(text "1" (rect -94 -64 -89 -47)(font "Intel Clear" ))
|
||||
(pt -80 -48)
|
||||
(pt -104 -48)
|
||||
)
|
||||
(connector
|
||||
(pt -200 160)
|
||||
(pt -248 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -200 -8)
|
||||
(pt -80 -8)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -256 304)
|
||||
(pt -160 304)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -160 40)
|
||||
(pt -80 40)
|
||||
|
|
@ -840,26 +807,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt -200 384)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -160 40)
|
||||
(pt -160 304)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -160 304)
|
||||
(pt -160 432)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 992 104)
|
||||
(pt 1024 104)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 976 152)
|
||||
(pt 1024 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 1184 128)
|
||||
(pt 1224 128)
|
||||
|
|
@ -930,38 +882,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
(pt 728 440)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
|
||||
(pt 520 -16)
|
||||
(pt 688 -16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 976 16)
|
||||
(pt 976 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 944 16)
|
||||
(pt 976 16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 944 -16)
|
||||
(pt 992 -16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 992 104)
|
||||
(pt 992 -16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
|
||||
(pt 528 16)
|
||||
(pt 688 16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 688 48)
|
||||
(pt 488 48)
|
||||
|
|
@ -973,43 +898,99 @@ https://fpgasoftware.intel.com/eula.
|
|||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "DIFF[7..0]" (rect 106 392 150 409)(font "Intel Clear" ))
|
||||
(pt 96 408)
|
||||
(pt 152 408)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "D[7..0]" (rect 474 232 504 249)(font "Intel Clear" ))
|
||||
(pt 464 248)
|
||||
(pt 512 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "DIFF[7..0]" (rect 282 232 326 249)(font "Intel Clear" ))
|
||||
(pt 312 248)
|
||||
(pt 272 248)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "B[7..0]" (rect 530 456 560 473)(font "Intel Clear" ))
|
||||
(pt 520 472)
|
||||
(pt 800 472)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "DIFF[7]" (rect 298 456 332 473)(font "Intel Clear" ))
|
||||
(pt 360 472)
|
||||
(pt 288 472)
|
||||
)
|
||||
(connector
|
||||
(text "A[7..0]" (rect 298 472 328 489)(font "Intel Clear" ))
|
||||
(pt 360 488)
|
||||
(pt 288 488)
|
||||
(text "D[7..0]" (rect 106 392 136 409)(font "Intel Clear" ))
|
||||
(pt 96 408)
|
||||
(pt 152 408)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "B[7..0]" (rect 298 488 328 505)(font "Intel Clear" ))
|
||||
(pt 360 504)
|
||||
(pt 288 504)
|
||||
(pt -360 224)
|
||||
(pt -320 224)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -320 224)
|
||||
(pt -320 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "A[7..0]" (rect -262 144 -232 161)(font "Intel Clear" ))
|
||||
(pt -320 160)
|
||||
(pt -200 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -544 224)
|
||||
(pt -584 224)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -544 240)
|
||||
(pt -584 240)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "0,S[7..1]" (rect 530 -40 567 -23)(font "Intel Clear" ))
|
||||
(pt 520 -16)
|
||||
(pt 688 -16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "0,D[7..1]" (rect 538 0 576 17)(font "Intel Clear" ))
|
||||
(pt 528 16)
|
||||
(pt 688 16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 944 -16)
|
||||
(pt 992 -16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 944 16)
|
||||
(pt 976 16)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 976 16)
|
||||
(pt 976 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 976 152)
|
||||
(pt 1024 152)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -360 240)
|
||||
(pt -344 240)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -344 240)
|
||||
(pt -344 304)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "B[7..0]" (rect -270 288 -240 305)(font "Intel Clear" ))
|
||||
(pt -160 304)
|
||||
(pt -344 304)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -160 40)
|
||||
(pt -160 304)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt -160 304)
|
||||
(pt -160 432)
|
||||
(bus)
|
||||
)
|
||||
(junction (pt -200 160))
|
||||
|
|
|
|||
25
mul8.bsf
25
mul8.bsf
|
|
@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
|
|||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
|
|
@ -16,12 +16,11 @@ the Intel FPGA IP License Agreement, or other applicable license
|
|||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 184 112)
|
||||
(rect 16 16 216 112)
|
||||
(text "mul8" (rect 5 0 35 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 75 24 92)(font "Intel Clear" ))
|
||||
(port
|
||||
|
|
@ -34,25 +33,25 @@ https://fpgasoftware.intel.com/eula.
|
|||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "A[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "A[7..0]" (rect 21 43 59 62)(font "Intel Clear" (font_size 8)))
|
||||
(text "NUM1[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "NUM1[7..0]" (rect 21 43 89 62)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "B[7..0]" (rect 0 0 38 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "B[7..0]" (rect 21 59 59 78)(font "Intel Clear" (font_size 8)))
|
||||
(text "NUM2[7..0]" (rect 0 0 68 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "NUM2[7..0]" (rect 21 59 89 78)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(pt 200 32)
|
||||
(output)
|
||||
(text "PROD[15..0]" (rect 0 0 74 19)(font "Intel Clear" (font_size 8)))
|
||||
(text "PROD[15..0]" (rect 73 27 147 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32)(line_width 3))
|
||||
(text "PROD[15..0]" (rect 105 27 179 46)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 200 32)(pt 184 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
(rectangle (rect 16 16 184 80))
|
||||
)
|
||||
)
|
||||
|
|
|
|||
19
mux_3x16.v
19
mux_3x16.v
|
|
@ -1,19 +0,0 @@
|
|||
module mux_3x16 (s, in0, in1, in2, result);
|
||||
|
||||
input [1:0]s;
|
||||
input [15:0]in0;
|
||||
input [15:0]in1;
|
||||
input [15:0]in2;
|
||||
|
||||
output reg [15:0]result;
|
||||
|
||||
always @(*) begin
|
||||
case(s)
|
||||
2'b00: result = in0;
|
||||
2'b01: result = in1;
|
||||
2'b10: result = in2;
|
||||
default: result = in0;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
module mux_3x16 (s, in0, in1, in2, result);
|
||||
|
||||
input [1:0]s;
|
||||
input [15:0]in0;
|
||||
input [15:0]in1;
|
||||
input [15:0]in2;
|
||||
|
||||
output reg [15:0]result;
|
||||
|
||||
always @(*) begin
|
||||
case(s)
|
||||
2'b00: result = in0;
|
||||
2'b01: result = in1;
|
||||
2'b10: result = in2;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in a new issue