Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog
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2020-05-27 18:53:59 +01:00
.gitignore Finished decoder 2020-05-27 18:53:03 +01:00
CPUProject.bdf Revisions for testing 2020-05-27 18:53:59 +01:00
CPUProject.qpf Basic Project Setup 2020-05-20 12:44:57 +01:00
CPUProject.qsf Finished decoder 2020-05-27 18:53:03 +01:00
data.mif Finished decoder 2020-05-27 18:53:03 +01:00
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LUTSquares.mif Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
mux_8x16.bdf Working on initial design 2020-05-25 17:16:24 +01:00
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ram_data.bsf Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.qip Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.v Finished decoder 2020-05-27 18:53:03 +01:00
ram_instr.bsf Working on datapath 2020-05-27 11:10:13 +01:00
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ram_instr.v Finished decoder 2020-05-27 18:53:03 +01:00
README.md Initial commit 2020-05-20 12:05:19 +01:00
reg_file.bdf Finished datapath 2020-05-25 18:00:34 +01:00
reg_file.bsf Working on initial design 2020-05-25 17:16:24 +01:00
SM.bdf Working on datapath 2020-05-27 11:10:13 +01:00
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SquareMIFGenerator.cpp Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00

CPUProject