supleed2/ELEC40006-P1-CW
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Yr1 Summer Term Project, ARM-based CPU designed to be simulated in Icarus Verilog
22 commits 1 branch 0 tags 69 MiB
Verilog 81.9%
C++ 17.8%
Tcl 0.3%
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Aadi Desai 08a8635959 Updated ALU to use internal carry register 
Also tidied up begin/end tags to reduce number of lines and improve readability
2020-06-04 15:05:13 +01:00
.gitignore Almost completed 16 bit multiplier. 2020-05-28 15:02:22 -07:00
abs.bdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
abs.bsf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
alu.v Updated ALU to use internal carry register 2020-06-04 15:05:13 +01:00
alu.v.bak ALU now uses multiply block rather than * operator 2020-06-03 15:15:44 +01:00
CPUProject.bdf Fixed decoder and SM 2020-06-02 20:09:22 +01:00
CPUProject.qpf Basic Project Setup 2020-05-20 12:44:57 +01:00
CPUProject.qsf ALU now uses multiply block rather than * operator 2020-06-03 15:15:44 +01:00
CPUProject_assignment_defaults.qdf Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
data.mif Finished decoder 2020-05-27 18:53:03 +01:00
DECODE.bsf Fixed decoder and SM 2020-06-02 20:09:22 +01:00
DECODE.v Fixed decoder and SM 2020-06-02 20:09:22 +01:00
DECODE.v.bak Fixed decoder and SM 2020-06-02 20:09:22 +01:00
instr.mif Finished decoder 2020-05-27 18:53:03 +01:00
InstructionGenerator.cpp Added most of the code for generating the instruction MIF. Still need to do a big if-else statement for every instruction. 2020-05-28 14:42:02 -07:00
LUT.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUT.qip Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUT.v Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
LUTSquares.mif Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00
min.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
min.v.bak Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul8.bdf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul8.bsf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mul16.bdf Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
mux_8x16.bdf Working on initial design 2020-05-25 17:16:24 +01:00
mux_8x16.bsf Working on initial design 2020-05-25 17:16:24 +01:00
ram_data.bsf Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.qip Working on datapath 2020-05-27 11:10:13 +01:00
ram_data.v Finished decoder 2020-05-27 18:53:03 +01:00
ram_instr.bsf Working on datapath 2020-05-27 11:10:13 +01:00
ram_instr.qip Working on datapath 2020-05-27 11:10:13 +01:00
ram_instr.v Finished decoder 2020-05-27 18:53:03 +01:00
README.md Initial commit 2020-05-20 12:05:19 +01:00
reg_file.bdf Finished datapath 2020-05-25 18:00:34 +01:00
reg_file.bsf Working on initial design 2020-05-25 17:16:24 +01:00
SM.bsf Fixed decoder and SM 2020-06-02 20:09:22 +01:00
SM.v Fixed decoder and SM 2020-06-02 20:09:22 +01:00
SM.v.bak Fixed decoder and SM 2020-06-02 20:09:22 +01:00
SquareMIFGenerator.cpp Added the look-up table and the code used to generate it 2020-05-25 22:47:29 +01:00

README.md

CPUProject