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23 lines
413 B
Verilog
23 lines
413 B
Verilog
module SM
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(
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input CLK,
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input E2,
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output FETCH,
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output EXEC1,
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output EXEC2
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);
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reg [2:0]s = 3'b1; //current state initialised to 001
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always @(posedge CLK) //Change on rising edge of clock
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begin
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s[2] <= ~s[2] & s[1] & ~s[0] & E2;
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s[1] <= ~s[2] & ~s[1] & s[0];
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s[0] <= (~s[2] & s[1] & ~s[0] & ~E2) | (s[2] & ~s[1] & ~s[0]);
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end
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assign FETCH = s[0];
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assign EXEC1 = s[1];
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assign EXEC2 = s[2];
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endmodule
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