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.gitignore
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Added new test mif with no multiplication
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2020-06-08 13:13:26 +01:00 |
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abs.bdf
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Started working on the multiply block. Added absolute value block.
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2020-05-28 09:11:14 -07:00 |
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abs.bsf
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Started working on the multiply block. Added absolute value block.
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2020-05-28 09:11:14 -07:00 |
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ADD_1.bsf
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Added pipelined SM and block needed for pipelining
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2020-06-09 15:49:41 +01:00 |
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ADD_1.v
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Added pipelined SM and block needed for pipelining
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2020-06-09 15:49:41 +01:00 |
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ADD_1.v.bak
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Added pipelined SM and block needed for pipelining
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2020-06-09 15:49:41 +01:00 |
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all_instr_test.mif
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Fixed instrGen and added large test
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2020-06-07 17:41:37 +01:00 |
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all_instr_test.txt
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Fixed instrGen and added large test
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2020-06-07 17:41:37 +01:00 |
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alu.bsf
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Added LDR and STR to alu and set up data paths
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2020-06-10 14:02:15 +01:00 |
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alu.v
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Added LDR and STR to alu and set up data paths
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2020-06-10 14:02:15 +01:00 |
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alu.v.bak
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ALU now uses multiply block rather than * operator
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2020-06-03 15:15:44 +01:00 |
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ALU_top.bdf
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Added LDR and STR to alu and set up data paths
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2020-06-10 14:02:15 +01:00 |
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ALU_top.bsf
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Added LDR and STR to alu and set up data paths
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2020-06-10 14:02:15 +01:00 |
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CPUProject.bdf
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Added decoder logic for STR and LDR
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2020-06-10 14:40:58 +01:00 |
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CPUProject.qpf
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Basic Project Setup
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2020-05-20 12:44:57 +01:00 |
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CPUProject.qsf
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Added decoder logic for STR and LDR
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2020-06-10 14:40:58 +01:00 |
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CPUProject.qws
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Added decoder logic for STR and LDR
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2020-06-10 14:40:58 +01:00 |
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CPUProject_assignment_defaults.qdf
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Started working on the multiply block. Added absolute value block.
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2020-05-28 09:11:14 -07:00 |
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data.mif
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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DECODE.bsf
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Added decoder logic for STR and LDR
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2020-06-10 14:40:58 +01:00 |
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DECODE.v
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Added decoder logic for STR and LDR
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2020-06-10 14:40:58 +01:00 |
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DECODE.v.bak
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Fixed decoder and SM
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2020-06-02 20:09:22 +01:00 |
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Initial MUX 8x16 design.PNG
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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instr.mif
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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InstructionGenerator.cpp
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Added STR and LDR to the cpp generator
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2020-06-10 13:00:40 +01:00 |
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LIFOstack.bsf
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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LIFOstack.v
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Update LIFOstack to support 32 memory slots
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2020-06-07 20:05:46 +01:00 |
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LIFOstack.v.bak
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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LUT.bsf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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LUT.qip
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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LUT.v
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Updated LUT to have an unregistered output
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2020-06-09 20:33:10 +01:00 |
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LUT_bb.v
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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LUTSquares.mif
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Added the look-up table and the code used to generate it
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2020-05-25 22:47:29 +01:00 |
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min.bsf
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Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available
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2020-05-29 09:47:44 -07:00 |
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min.v
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Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available
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2020-05-29 09:47:44 -07:00 |
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min.v.bak
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Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available
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2020-05-29 09:47:44 -07:00 |
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mul8.bdf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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mul8.bsf
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Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available
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2020-05-29 09:47:44 -07:00 |
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mul16.bdf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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mul16.bsf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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mux_3x16.bsf
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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mux_3x16.v
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Recompiled certain files
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2020-06-08 12:10:14 +01:00 |
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mux_3x16.v.bak
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Recompiled certain files
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2020-06-08 12:10:14 +01:00 |
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mux_8x16.bsf
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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mux_8x16.v
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Recompiled certain files
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2020-06-08 12:10:14 +01:00 |
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mux_8x16.v.bak
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Almost ready CPU
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2020-06-07 15:08:34 +01:00 |
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ram_data.bsf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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ram_data.qip
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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ram_data.v
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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ram_instr.bsf
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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ram_instr.qip
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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ram_instr.v
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Final State before Pipelining
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2020-06-09 22:45:20 +01:00 |
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README.md
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Initial commit
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2020-05-20 12:05:19 +01:00 |
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reg_file.bdf
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Debugging CPU
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2020-06-07 20:51:33 +01:00 |
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reg_file.bsf
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Working on initial design
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2020-05-25 17:16:24 +01:00 |
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SM.bsf
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Debugging CPU
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2020-06-07 20:51:33 +01:00 |
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SM.v
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Debugging complete!
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2020-06-08 23:07:52 +01:00 |
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SM.v.bak
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Fixed decoder and SM
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2020-06-02 20:09:22 +01:00 |
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SM_pipelined.v
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Added pipelined SM and block needed for pipelining
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2020-06-09 15:49:41 +01:00 |
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SM_pipelined.v.bak
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Added pipelined SM and block needed for pipelining
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2020-06-09 15:49:41 +01:00 |
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SquareMIFGenerator.cpp
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Added the look-up table and the code used to generate it
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2020-05-25 22:47:29 +01:00 |
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test_no_mul.mif
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Added new test mif with no multiplication
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2020-06-08 13:13:26 +01:00 |
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test_no_mul.txt
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Update test_no_mul.txt
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2020-06-09 12:11:06 +01:00 |
