supleed2/ELEC40006-P1-CW
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24 commits

Author SHA1 Message Date
Aadi Desai 87f3d0e919 CPU set up for testing and analysis 2020-06-11 17:28:00 +01:00
Aadi Desai 4688a56452 Modified Test Program to add LDR and STR 
Also fixed logic within decoder for LDR and STR
 2020-06-10 15:51:51 +01:00
Kacper 719c9ede2b Added decoder logic for STR and LDR 2020-06-10 14:40:58 +01:00
Aadi Desai d046242bc1 Final State before Pipelining 
Debug Complete, data and instruction mifs + ram files. Test program checked
 2020-06-09 22:45:20 +01:00
Kacper 20f2adc4a1 Removed some waveform and test files 2020-06-09 19:01:55 +01:00
Kacper 46282576df Added pipelined SM and block needed for pipelining 2020-06-09 15:49:41 +01:00
Kacper 2f6cbeae56 Debugging complete! 
The CPU works now except for the multiply commands. Pipelining is next! Woooo!
 2020-06-08 23:07:52 +01:00
Kacper 24b293e24b Recompiled certain files 2020-06-08 12:10:14 +01:00
Kacper 3d9ea175cd Working on debugging 
The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.
 2020-06-07 23:23:13 +01:00
Kacper b527d5e77d Debugging CPU 2020-06-07 20:51:33 +01:00
Kacper 9a1a1da664 Complete CPU v2 (not tested) 2020-06-07 16:12:05 +01:00
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Kacper 4318a5b70b CPU completed 2020-06-04 16:33:27 +01:00
Aadi Desai 3647e0b15c ALU now uses multiply block rather than * operator 
Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input
 2020-06-03 15:15:44 +01:00
Kacper 1c0032fa95 Fixed decoder and SM 2020-06-02 20:09:22 +01:00
ben 5d6c9803fc Implemented multiplication fully. 16 bits and 8 bits multiplier circuits available 2020-05-29 09:47:44 -07:00
ben 3d6e456fcc Almost completed 16 bit multiplier. 2020-05-28 15:02:22 -07:00
ben e39d2f653a Started working on the multiply block. Added absolute value block. 2020-05-28 09:11:14 -07:00
Kacper e1acb56b66 Finished decoder 2020-05-27 18:53:03 +01:00
Kacper 5ed70dabb0 Working on datapath 2020-05-27 11:10:13 +01:00
Kacper 3b298e02a2 Finished datapath 2020-05-25 18:00:34 +01:00
Kacper 6b2363d6a1 Working on initial design 2020-05-25 17:16:24 +01:00
Benjamin 14418c8725 VCS Test 2020-05-20 19:24:20 +01:00
Aadi Desai 26c28a829d Basic Project Setup 2020-05-20 12:44:57 +01:00