mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-09-19 20:26:18 +00:00
71 lines
3.4 KiB
Plaintext
71 lines
3.4 KiB
Plaintext
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
# Your use of Intel Corporation's design tools, logic functions
|
|
# and other software and tools, and its AMPP partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Intel Program License
|
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
# the Intel FPGA IP License Agreement, or other applicable license
|
|
# agreement, including, without limitation, that your use is for
|
|
# the sole purpose of programming logic devices manufactured by
|
|
# Intel and sold by Intel or its authorized distributors. Please
|
|
# refer to the applicable agreement for further details.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Quartus Prime
|
|
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
|
# Date created = 12:38:12 May 20, 2020
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Notes:
|
|
#
|
|
# 1) The default values for assignments are stored in the file:
|
|
# CPUProject_assignment_defaults.qdf
|
|
# If this file doesn't exist, see file:
|
|
# assignment_defaults.qdf
|
|
#
|
|
# 2) Altera recommends that you do not modify this file. This
|
|
# file is updated automatically by the Quartus Prime software
|
|
# and any changes you make may be lost or overwritten.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
|
|
|
|
set_global_assignment -name FAMILY "Cyclone IV E"
|
|
set_global_assignment -name DEVICE AUTO
|
|
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
|
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
set_global_assignment -name VERILOG_FILE LIFOstack.v
|
|
set_global_assignment -name VERILOG_FILE alu.v
|
|
set_global_assignment -name MIF_FILE LUTSquares.mif
|
|
set_global_assignment -name BDF_FILE mul8.bdf
|
|
set_global_assignment -name BDF_FILE abs.bdf
|
|
set_global_assignment -name BDF_FILE CPUProject.bdf
|
|
set_global_assignment -name BDF_FILE reg_file.bdf
|
|
set_global_assignment -name QIP_FILE ram_data.qip
|
|
set_global_assignment -name QIP_FILE ram_instr.qip
|
|
set_global_assignment -name VERILOG_FILE DECODE.v
|
|
set_global_assignment -name MIF_FILE data.mif
|
|
set_global_assignment -name MIF_FILE instr.mif
|
|
set_global_assignment -name BDF_FILE mul16.bdf
|
|
set_global_assignment -name QIP_FILE LUT.qip
|
|
set_global_assignment -name VERILOG_FILE min.v
|
|
set_global_assignment -name VERILOG_FILE SM.v
|
|
set_global_assignment -name BDF_FILE ALU_top.bdf
|
|
set_global_assignment -name VERILOG_FILE mux_8x16.v
|
|
set_global_assignment -name VERILOG_FILE mux_3x16.v
|
|
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |