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685f69a7cf
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
69 lines
3.3 KiB
Plaintext
69 lines
3.3 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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# Date created = 12:38:12 May 20, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# CPUProject_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY mux_8x16
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_FILE alu.v
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set_global_assignment -name MIF_FILE LUTSquares.mif
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set_global_assignment -name BDF_FILE mul8.bdf
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set_global_assignment -name BDF_FILE abs.bdf
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set_global_assignment -name BDF_FILE CPUProject.bdf
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set_global_assignment -name BDF_FILE reg_file.bdf
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set_global_assignment -name QIP_FILE ram_data.qip
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set_global_assignment -name QIP_FILE ram_instr.qip
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set_global_assignment -name VERILOG_FILE DECODE.v
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set_global_assignment -name MIF_FILE data.mif
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set_global_assignment -name MIF_FILE instr.mif
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set_global_assignment -name BDF_FILE mul16.bdf
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set_global_assignment -name QIP_FILE LUT.qip
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set_global_assignment -name VERILOG_FILE min.v
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set_global_assignment -name VERILOG_FILE SM.v
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set_global_assignment -name BDF_FILE ALU_top.bdf
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set_global_assignment -name VERILOG_FILE mux_8x16.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VERILOG_FILE mux_3x16.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |