Alden0012
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3c60629d48
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Add scripts/rtl for formal verification
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2022-12-16 20:19:07 +00:00 |
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Aadi Desai
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827ed444fa
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Fixes and adding missing setup.do script for vsim
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2022-12-12 16:49:07 +00:00 |
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Alden0012
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aabd220e6a
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Increase covergroups and test inputs for VGA, Integrate gpio checker in tb
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2022-12-12 16:16:17 +00:00 |
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Alden0012
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f586cd95d9
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Add VGA and GPIO checker
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2022-12-05 16:55:23 +00:00 |
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Alden0012
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128a2a9eaa
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Fix GPIO assertions and test-bench coverage and constraints
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2022-11-14 15:28:45 +00:00 |
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Alden0012
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f50d0c5c2e
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Add redundant VGA and comparator module
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2022-11-08 17:49:23 +00:00 |
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Alden0012
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4edfce0e03
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Add initial assume to AHBGPIO.sv
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2022-11-08 17:27:39 +00:00 |
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Alden0012
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0f8578e1b8
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Add assertions to AHBGPIO.sv
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2022-11-08 17:04:59 +00:00 |
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Aadi Desai
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0d4099ce15
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Update AHBVGASYS.sv to SystemVerilog and style
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2022-11-07 13:57:19 +00:00 |
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Aadi Desai
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018013d3c8
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Add parity generation and checking to AHBGPIO.sv
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2022-11-07 13:36:56 +00:00 |
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Aadi Desai
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c83b8a73f1
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Switch all Verilog files to SystemVerilog file endings
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2022-11-07 12:58:43 +00:00 |
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Aadi Desai
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dcdda4d9e1
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Initial Commit
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2022-11-07 12:41:05 +00:00 |
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