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  • 2534edabe3 Finish Docs main Aadi Desai 2020-12-21 21:16:28 +0000
  • 8ec142585b Added Diagram related files, and Datasheet update jc4419 2020-12-21 19:48:52 +0400
  • 3291163ed2 Fix collision between scripts/remaining files from previous run Aadi Desai 2020-12-20 08:54:04 -0800
  • 6637ad813f Rename vcd to differentiate between bus and harvard Aadi Desai 2020-12-20 08:46:29 -0800
  • 86656b33ef Set harvard_tb clk_enable high, to allow other CPUs to run Aadi Desai 2020-12-20 08:44:05 -0800
  • 859020bae5 Add testcase specific waveforms Aadi Desai 2020-12-20 08:42:37 -0800
  • 9003384106 Fix sltiu in control, sb/sh instr and add jr 31 instr jl7719 2020-12-20 14:32:49 +0000
  • 711d0df54e Update files to remove random Quartus errors Quartus_ready Aadi Desai 2020-12-20 12:43:19 +0000
  • 7b01ae06eb Change parameter to use instr+data testcase Aadi Desai 2020-12-20 12:08:21 +0000
  • 62c7ffc32b updated ref ibzmo 2020-12-20 10:32:11 +0000
  • f8dbdeaccd minor correction ibzmo 2020-12-20 10:31:18 +0000
  • 3dce72e26c Add more testcase for srav, srlv jl7719 2020-12-20 09:23:22 +0000
  • d3dcd92a44 Fix sllv, srlv, srav to shift by A[4:0] jl7719 2020-12-20 09:07:35 +0000
  • 1458a6c619 testcase fix 3 yhp19 2020-12-20 16:29:24 +0800
  • 861e7899fe testcase fix 2 yhp19 2020-12-20 16:03:43 +0800
  • 86dcf34d6e testcase error fix yhp19 2020-12-20 15:55:15 +0800
  • 81f720d03f last extra testcases yhp19 2020-12-20 15:30:20 +0800
  • 088b2bae21 Replace .v with .sv in scripts to match Aadi Desai 2020-12-19 15:59:27 +0000
  • 6c0554538c Rename .v to .sv for Quartus to detect as SystemVerilog Aadi Desai 2020-12-19 15:58:00 +0000
  • 7a09c7e9f7 Add sb testcase jl7719 2020-12-19 16:05:44 +0000
  • f56d61f2f3 Remove enum from alu.v using find&replace Aadi Desai 2020-12-19 07:52:50 -0800
  • 76fbc7d5c4 Remove enum from control.v using find&replace Aadi Desai 2020-12-19 15:40:29 +0000
  • 85e23d824c Add more testcases for mthi, mtlo, mult, multu jl7719 2020-12-19 15:34:35 +0000
  • 0d731c74b2 Add testcases for or and ori jl7719 2020-12-19 13:13:56 +0000
  • 7850cb65d6 fixing testcase errors theexecutor13 2020-12-19 11:16:39 +0000
  • 3836be459f Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main yhp19 2020-12-19 19:04:39 +0800
  • cbc305b139 load instr testcase yhp19 2020-12-19 19:04:29 +0800
  • 8d100e8693 Update regfile and harvard to enable register reset jl7719 2020-12-19 10:55:41 +0000
  • cecf5537b0 Fix some errors jl7719 2020-12-19 10:41:05 +0000
  • 49b7fdbe07
         Update Harvard for new regfile input Aadi Desai 2020-12-19 10:27:17 +0000
  • a598321539
         Use base+offset[1:0] for partial loads instead of base[1:0] Aadi Desai 2020-12-19 10:22:44 +0000
  • 6797fc5a32 added some jump testcases yhp19 2020-12-19 15:24:34 +0800
  • 3110fb19ea fixed branch instr testcase theexecutor13 2020-12-19 06:32:51 +0000
  • ce776e28ce added more branch instructions testcases yhp19 2020-12-19 14:15:44 +0800
  • 9aa405120f Fix divu testcases and add divu-5 testcase jl7719 2020-12-19 05:37:54 +0000
  • 88eadf4f27 reference to with these instructions ibzmo 2020-12-18 23:15:04 +0000
  • 044e972176 sll, sllv & store and set instructions still to go ibzmo 2020-12-18 23:13:47 +0000
  • ea21975708 fixing testcases theexecutor13 2020-12-18 15:04:46 +0000
  • 9e7a5caf82 weird cases added yhp19 2020-12-18 23:10:15 +0800
  • 3e5729e642 beq testcases yhp19 2020-12-18 22:08:55 +0800
  • a59e73f746 Fix test script not being able to find src dir jl7719 2020-12-18 12:51:53 +0000
  • a31d41512b Rename all instruction mem init files to .instr.txt jl7719 2020-12-18 12:42:58 +0000
  • dd4f6346be Add exec folder and executable.txt back for the test to work jl7719 2020-12-18 10:51:30 +0000
  • b114d87cf3 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main Merge jl7719 2020-12-18 10:41:44 +0000
  • a4a28db189 Add stderr.txt files and diff.txt files for debugging jl7719 2020-12-18 10:41:01 +0000
  • bcc05cd061 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main theexecutor13 2020-12-18 10:07:54 +0000
  • 3f8393a404 add some testcases theexecutor13 2020-12-18 10:07:42 +0000
  • 4f97fb41d8 Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v jl7719 2020-12-18 09:55:41 +0000
  • f3779e1cc3 Fix div-5 testcase minor error jl7719 2020-12-18 09:24:58 +0000
  • 2a7b9c2c49 Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main jl7719 2020-12-18 09:22:27 +0000
  • 47a452cd6d Fix div input testcases 3,4,5 jl7719 2020-12-18 09:20:00 +0000
  • 339e2b6b58 updated ref ibzmo 2020-12-18 09:15:58 +0000
  • 579dc5e008 fixed one test case Ibrahim 2020-12-18 09:10:46 +0000
  • c13ed23d90 ref file for these test cases - will add complete ref file for all edge cases soon Ibrahim 2020-12-18 08:51:53 +0000
  • 48e0cdfbb6 added edge cases these don't pass - please check Ibrahim 2020-12-18 08:48:51 +0000
  • 099540f6ec
         Merge pull request #2 from supleed2/bus_wrapper Aadi Desai 2020-12-17 18:25:17 +0000
  • 1be11d6c19 Add second store halfword testcase Aadi Desai 2020-12-17 09:52:51 -0800
  • 5c29ec2be1 Shorten testbench limit, remove custom bus script Aadi Desai 2020-12-17 09:44:31 -0800
  • e513096ed8 Add missing opcodes to CtrlMemRead = 0 Aadi Desai 2020-12-17 09:43:47 -0800
  • 6687cb8e17 Bring read signal low with clk during read cycle Aadi Desai 2020-12-17 09:43:04 -0800
  • c8344184b2 Fix sb, sh testcases Aadi Desai 2020-12-17 09:41:25 -0800
  • ad394c7d7d Adding missing opcodes to CtrlMemRead Aadi Desai 2020-12-17 09:02:58 -0800
  • cb29efd034 Merge branch 'main' into bus_wrapper Aadi Desai 2020-12-17 16:46:01 +0000
  • 2be1978a36 Add initial value to npc, add JR to CtrlMemRead Aadi Desai 2020-12-17 08:43:58 -0800
  • 1ae5d78b4d Added dummy clk_enable to harvard instance, added clock kickstart after reset Aadi Desai 2020-12-17 07:58:33 -0800
  • 74681e8890 Stall bus memory when reset is high Aadi Desai 2020-12-17 07:34:32 -0800
  • cfebb403ba Delete from source files and the testbench jl7719 2020-12-17 15:02:59 +0000
  • 2d9cca262d Fix display appearing at the end of log file jl7719 2020-12-17 14:51:08 +0000
  • e89087c127 Bus Memory typo in bus script Aadi Desai 2020-12-17 06:34:42 -0800
  • 6c400f3567 uploading log.txt weirdness testcase theexecutor13 2020-12-17 14:31:33 +0000
  • 2eccc5148e Move bus memory from rtl to testbench folder Aadi Desai 2020-12-17 13:58:07 +0000
  • af29f22651 Merge branch 'main' into bus_wrapper Aadi Desai 2020-12-17 13:54:26 +0000
  • 0bdbb63f49
         Update reference.txt theexecutor13 2020-12-17 21:37:17 +0800
  • 7fcc2486cb cleanup theexecutor13 2020-12-17 13:37:00 +0000
  • ab13c84ef5 testing branch delay slot theexecutor13 2020-12-17 12:03:30 +0000
  • 4ab4809a8a restructuring theexecutor13 2020-12-17 11:47:13 +0000
  • 15dfce09c9
         Update reference.txt theexecutor13 2020-12-17 19:44:23 +0800
  • 6e626c5931 Change location of the memory module from rtl to testbench jl7719 2020-12-17 10:32:52 +0000
  • 33bb4c7538 Constant selects not working in always_ff in current iverilog Aadi Desai 2020-12-16 14:13:54 -0800
  • 5e62dd82d8 Add bus vcd to gitignore, fix missing case in bus Aadi Desai 2020-12-16 14:08:28 -0800
  • d17060b0a1 Add missing end to if statement Aadi Desai 2020-12-16 13:54:01 -0800
  • da0c9aba01 Fix {} for bit duplication, remove module name from endmodule Aadi Desai 2020-12-16 13:38:09 -0800
  • 744aee097f Modify bus tb to compile bus version instead Aadi Desai 2020-12-16 20:15:08 +0000
  • 4534ca6760 Add custom test script for bus tb Aadi Desai 2020-12-16 20:09:08 +0000
  • 2f9b08a363 Updated bus tb to match harvard tb Aadi Desai 2020-12-16 20:05:00 +0000
  • a31ed073e1 Merge branch 'main' into bus_wrapper Aadi Desai 2020-12-16 19:57:28 +0000
  • 20880f6ab2 Complete avalon bus memory Aadi Desai 2020-12-16 19:20:48 +0000
  • 697b6e0a9e Update some testcases for branch delay slots jl7719 2020-12-16 17:13:39 +0000
  • ec275418b7 Update harvard testbench regarding resets jl7719 2020-12-16 16:59:28 +0000
  • 1f7027f771 Update harvard test script to match spec jl7719 2020-12-16 16:46:27 +0000
  • f5fea77ea7 General structure of bus memory Aadi Desai 2020-12-16 08:42:26 -0800
  • 4be3149300 Update test_mips_cpu_bus.sh jl7719 2020-12-16 15:58:03 +0000
  • d8c918c9b4 Merge branch 'main' into bus_wrapper Aadi Desai 2020-12-16 15:41:56 +0000
  • 252f630162 Cleanup Aadi Desai 2020-12-16 15:40:21 +0000
  • 1a413d9686 Merge branch 'main' into jl7719 Aadi Desai 2020-12-16 15:40:07 +0000
  • ebe33ce56a Passes all tests jl7719 2020-12-16 15:29:04 +0000
  • 7185f7e7e6 Fixed BGEZAL Jeevaha Coelho 2020-12-16 07:00:46 -0800
  • 67682ecfde Create basic bus memory block Aadi Desai 2020-12-16 14:07:43 +0000
  • 2673e23137 FIxed PC! Jeevaha Coelho 2020-12-16 05:21:57 -0800
  • ad68ab0974 Debugging and debugging jl7719 2020-12-16 12:29:22 +0000