Add missing end to if statement

2024-12-22 21:35:48 +00:00 · 2020-12-16 13:54:01 -08:00 · 2020-12-16 13:54:01 -08:00 · d17060b0a1
parent da0c9aba01
commit d17060b0a1
1 changed files with 1 additions and 0 deletions
--- a/rtl/mips_cpu_bus_memory.v
+++ b/rtl/mips_cpu_bus_memory.v
@ -75,6 +75,7 @@ always_ff @(posedge clk) begin
                    data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0];
                end
                waitrequest <= 1'b0; // end with setting waitrequest low
+            end
        end else begin
            waitrequest <= 1'bx;
            readdata <= 32'hxxxxxxxx;