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https://github.com/supleed2/ELEC50010-IAC-CW.git
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Fix sltiu in control, sb/sh instr and add jr 31 instr
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parent
62c7ffc32b
commit
9003384106
4
inputs/addiu/addiu-3.instr.txt
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4
inputs/addiu/addiu-3.instr.txt
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@ -0,0 +1,4 @@
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25080000
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03e00008
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25080000
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00000000
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1
inputs/addiu/addiu-3.ref.txt
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1
inputs/addiu/addiu-3.ref.txt
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@ -0,0 +1 @@
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0
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@ -1,5 +1,5 @@
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3C041234
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34045678
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34845678
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3405101C
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A0A40000
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80A20000
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@ -1,5 +1,5 @@
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3C041234
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34045678
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34845678
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3405101C
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A0A40000
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8CA20000
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@ -1,5 +1,5 @@
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3C041234
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34045678
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34845678
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3405101C
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A4A40000
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84A20000
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@ -1,5 +1,5 @@
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3C041234
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34045678
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34845678
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3405101C
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A4A40000
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8CA20000
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@ -1 +1 @@
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0
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1
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@ -207,7 +207,7 @@ always @(*) begin
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end else begin CtrlALUSrc = 1'bx;end
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//CtrlRegWrite logic
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if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
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if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTIU) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
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CtrlRegWrite = 1;//The Registers are Write Enabled
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end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
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end
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