diff --git a/inputs/addiu/addiu-3.instr.txt b/inputs/addiu/addiu-3.instr.txt
new file mode 100644
index 0000000..21f9d84
--- /dev/null
+++ b/inputs/addiu/addiu-3.instr.txt
@@ -0,0 +1,4 @@
+25080000
+03e00008
+25080000
+00000000
diff --git a/inputs/addiu/addiu-3.ref.txt b/inputs/addiu/addiu-3.ref.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/inputs/addiu/addiu-3.ref.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/inputs/sb/sb-1.instr.txt b/inputs/sb/sb-1.instr.txt
index c42c078..54ae57a 100644
--- a/inputs/sb/sb-1.instr.txt
+++ b/inputs/sb/sb-1.instr.txt
@@ -1,5 +1,5 @@
 3C041234
-34045678
+34845678
 3405101C
 A0A40000
 80A20000
diff --git a/inputs/sb/sb-2.instr.txt b/inputs/sb/sb-2.instr.txt
index 7989322..1803802 100644
--- a/inputs/sb/sb-2.instr.txt
+++ b/inputs/sb/sb-2.instr.txt
@@ -1,5 +1,5 @@
 3C041234
-34045678
+34845678
 3405101C
 A0A40000
 8CA20000
diff --git a/inputs/sh/sh-1.instr.txt b/inputs/sh/sh-1.instr.txt
index 2203c02..e9ff94c 100644
--- a/inputs/sh/sh-1.instr.txt
+++ b/inputs/sh/sh-1.instr.txt
@@ -1,5 +1,5 @@
 3C041234
-34045678
+34845678
 3405101C
 A4A40000
 84A20000
diff --git a/inputs/sh/sh-2.instr.txt b/inputs/sh/sh-2.instr.txt
index bbbbdf7..e956a54 100644
--- a/inputs/sh/sh-2.instr.txt
+++ b/inputs/sh/sh-2.instr.txt
@@ -1,5 +1,5 @@
 3C041234
-34045678
+34845678
 3405101C
 A4A40000
 8CA20000
diff --git a/inputs/sltiu/sltiu-2.ref.txt b/inputs/sltiu/sltiu-2.ref.txt
index c227083..56a6051 100644
--- a/inputs/sltiu/sltiu-2.ref.txt
+++ b/inputs/sltiu/sltiu-2.ref.txt
@@ -1 +1 @@
-0
\ No newline at end of file
+1
\ No newline at end of file
diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index af5d76f..371ea80 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -207,7 +207,7 @@ always @(*) begin
     end else begin CtrlALUSrc = 1'bx;end
        
     //CtrlRegWrite logic
-    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
+    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTIU) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
         CtrlRegWrite = 1;//The Registers are Write Enabled
     end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
 end