supleed2/ELEC50010-IAC-CW
1
0
Fork 0
mirror of https://github.com/supleed2/ELEC50010-IAC-CW.git synced 2024-09-19 19:46:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v

Browse source
This commit is contained in:
jl7719 2020-12-18 09:55:41 +00:00
parent f3779e1cc3
commit 4f97fb41d8
3 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
test/test_mips_cpu_harvard.sh
View file

@ -25,7 +25,7 @@ then
-s mips_cpu_harvard_tb \
-P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \
-P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
${SRC} 2> /dev/null
./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference
@ -46,7 +46,7 @@ else
-s mips_cpu_harvard_tb \
-P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \
-P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_harvard_memory.v\
${SRC} 2> /dev/null
./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference

2
testbench/mips_cpu_memory.v → testbench/mips_cpu_harvard_memory.v
View file

@ -1,4 +1,4 @@
module mips_cpu_memory(
module mips_cpu_harvard_memory(
input logic clk,
//Data Memory

2
testbench/mips_cpu_harvard_tb.v
View file

@ -7,7 +7,7 @@ module mips_cpu_harvard_tb;
logic clk, clk_enable, reset, active, data_read, data_write;
logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
mips_cpu_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst(
mips_cpu_harvard_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) ramInst(
.clk(clk),
.data_address(data_address),
.data_write(data_write),