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Change parameter to use instr+data testcase
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module mips_cpu_harvard_tb;
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parameter INSTR_INIT_FILE = "inputs/addiu.txt";
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parameter DATA_INIT_FILE = "inputs/addiu.data.txt";
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parameter INSTR_INIT_FILE = "inputs/lw/lw-1.instr.txt";
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parameter DATA_INIT_FILE = "inputs/lw/lw-1.data.txt";
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parameter TIMEOUT_CYCLES = 100;
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logic clk, clk_enable, reset, active, data_read, data_write;
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