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General structure of bus memory

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Read and Write logic to be added
This commit is contained in:
Aadi Desai 2020-12-16 08:42:26 -08:00
parent 4be3149300
commit f5fea77ea7
1 changed files with 23 additions and 2 deletions
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25
rtl/mips_cpu_bus_memory.v
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@ -12,8 +12,8 @@ module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave)
parameter INSTR_INIT_FILE = "";
parameter DATA_INIT_FILE = "";
reg [31:0] data_memory [0:63]; // location 0x00001000 onwards
reg [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards
logic [31:0] data_memory [0:63]; // location 0x00001000 onwards
logic [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards
initial begin
for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default
@ -45,4 +45,25 @@ initial begin
end
end
always_ff @(posedge read or posedge write) begin
waitrequest <= 1;
end
always_ff @(posedge clk) begin
if (waitrequest) begin
if (read) begin
// read code
end else if (write) begin
// write code
end else begin
waitrequest = 1'bx;
readdata = 32'hxxxxxxxx;
end
end else begin
waitrequest = 1'b0;
readdata = 32'h00000000;
end
end
endmodule