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69 lines
2 KiB
Verilog
69 lines
2 KiB
Verilog
module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave)
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input logic clk,
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input logic[31:0] address,
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input logic write,
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input logic read,
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output logic waitrequest,
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input logic[31:0] writedata,
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input logic[3:0] byteenable,
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output logic[31:0] readdata
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);
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parameter INSTR_INIT_FILE = "";
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parameter DATA_INIT_FILE = "";
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logic [31:0] data_memory [0:63]; // location 0x00001000 onwards
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logic [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards
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initial begin
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for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default
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data_memory[i] = 0;
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end
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for (integer i=0; i<$size(instr_memory); i++) begin //Initialise instr to zero by default
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instr_memory[i] = 0;
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end
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if (INSTR_INIT_FILE != "") begin //Load instr contents from file if specified
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$display("RAM: Loading RAM contents from %s", INSTR_INIT_FILE);
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$readmemh(INSTR_INIT_FILE, instr_memory);
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end
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for (integer i = 0; i<$size(instr_memory); i++) begin //Read out instr contents to log
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$display("byte +%h: %h", 32'hBFC00000+i*4, instr_memory[i]);
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end
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if (DATA_INIT_FILE != "") begin //Load data contents from file if specified
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$display("MEM: Loading MEM contents from %s", DATA_INIT_FILE);
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$readmemh(DATA_INIT_FILE, data_memory);
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end else begin
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$display("MEM FILE NOT GIVEN");
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end
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for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log
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$display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]);
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end
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end
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always_ff @(posedge read or posedge write) begin
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waitrequest <= 1;
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end
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always_ff @(posedge clk) begin
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if (waitrequest) begin
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if (read) begin
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// read code
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end else if (write) begin
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// write code
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end else begin
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waitrequest = 1'bx;
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readdata = 32'hxxxxxxxx;
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end
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end else begin
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waitrequest = 1'b0;
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readdata = 32'h00000000;
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end
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end
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endmodule |