Jeevaha Coelho
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2673e23137
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FIxed PC!
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2020-12-16 05:21:57 -08:00 |
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jl7719
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ad68ab0974
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Debugging and debugging
PC, Jump instr, branches
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2020-12-16 12:29:22 +00:00 |
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jl7719
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0891f7e653
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Debug mult/div to work
it works now
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2020-12-16 08:38:46 +00:00 |
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jl7719
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4ff160db1a
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Fix syntax errors from mult/div
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2020-12-16 05:04:45 +00:00 |
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Jeevaha Coelho
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90917f7566
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Updated PC, Harv, ALU, to work w/ MULT(U), DIV(U)
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2020-12-15 13:48:28 -08:00 |
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jl7719
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85efff275a
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Fix program counter taking two cycles for each instr
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2020-12-15 15:53:30 +00:00 |
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jl7719
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fc5c8a17f5
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Fix signed error in alu block
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2020-12-15 15:19:51 +00:00 |
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Jeevaha Coelho
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85ba783a69
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Fixed signing error in alu and added excel file
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2020-12-15 05:21:37 -08:00 |
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Jeevaha Coelho
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5df8a72ca1
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fixed naming convention errors in pc and harvard
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2020-12-15 03:16:01 -08:00 |
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jl7719
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51dbe68ea8
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Fix running on different environment issue
Now completely shifted to Ubuntu 18.04 setup should work for everyone
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2020-12-14 17:38:39 +00:00 |
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jl7719
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7150487472
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Rename initialisation files
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2020-12-13 14:54:53 +09:00 |
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jl7719
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943745a1e0
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Tested all that can be tested for now
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
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2020-12-13 14:40:16 +09:00 |
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jl7719
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c31344c55f
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More testcases, testing, debugging
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2020-12-13 01:25:36 +09:00 |
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jl7719
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14ad7fa0ce
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Update program counter
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
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2020-12-12 15:59:14 +09:00 |
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jl7719
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3594365a25
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Create branch jl7719
Can test for normal pc incrementing instr
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2020-12-11 19:45:13 +09:00 |
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jl7719
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7ffd8fb400
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Add testcases and ref outputs for addiu, and, andi
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2020-12-11 15:17:43 +09:00 |
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jl7719
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04b1ed4fed
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Update control and memory
Fixed some errors when testing
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2020-12-10 22:27:08 +09:00 |
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jl7719
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84adff2ed1
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Update memory
No longer need the massive memory
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2020-12-10 19:14:16 +09:00 |
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jc4419
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3a2fde81b2
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-09 16:27:20 +04:00 |
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jc4419
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4b8a56ee2f
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Fixed if logic for control
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2020-12-09 16:24:21 +04:00 |
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jl7719
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c5aed43ab4
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Update to test each instruction with a small memory
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2020-12-09 16:47:58 +09:00 |
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Aadi Desai
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6becea322f
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Update mips_cpu_regfile.v
Regfile should now compile, write is skipped if $0 is the destination register
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2020-12-08 13:23:08 +00:00 |
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jc4419
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9de2b59bbb
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Updated Harvard, ALU, PC, Control, and Regfile
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2020-12-08 01:46:01 +04:00 |
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jc4419
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8f5e582f33
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Updated ALU - Minor Syntax Fixes
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2020-12-07 18:18:19 +04:00 |
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jc4419
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2ab6ff12eb
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-07 15:55:12 +04:00 |
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jc4419
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9198c4f51b
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Updated ALU and Control
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2020-12-07 15:49:44 +04:00 |
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Aadi Desai
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d347475b64
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Update mips_cpu_regfile.v
lb, lbu, lh, lhu now select data according to address alignment
$0 is assigned to 0, may cause an error when written to, unknown.
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2020-12-06 17:42:23 +00:00 |
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jl7719
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c5167645e7
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Fix overall w.r.t iverilog compiler error
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2020-12-06 15:44:58 +09:00 |
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jc4419
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a2bcf3ed1b
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Updated ALU
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2020-12-05 23:37:01 +04:00 |
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jl7719
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56b5b1aa89
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-04 23:45:16 +09:00 |
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jl7719
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411f89110f
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Add testbench related files
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2020-12-04 23:44:48 +09:00 |
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Aadi Desai
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847bf92add
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Fix regfile hazard from storing when inputs change
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2020-12-02 19:13:41 +00:00 |
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Aadi Desai
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f2f8e05010
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PC logic updated
PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
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2020-12-02 17:23:28 +00:00 |
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jl7719
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10af46a352
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Update mips_cpu_memory.v
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2020-12-02 23:41:04 +09:00 |
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Ibrahim
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64b9d16776
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-02 14:34:35 +00:00 |
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Ibrahim
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1f1cb53352
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Changed From ALUZero to Cond
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2020-12-02 14:33:42 +00:00 |
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Ibrahim
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a56410ceae
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-
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2020-12-02 14:32:42 +00:00 |
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Aadi Desai
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2c967a910b
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Update mips_cpu_harvard.v
Fix typo + immediate already fed in via alu_in2
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2020-12-02 14:24:17 +00:00 |
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Ibrahim
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888bb7c822
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-02 14:05:59 +00:00 |
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Ibrahim
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b81c2c0952
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Minor sytax corrections
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2020-12-02 14:03:16 +00:00 |
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yhp19
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d1d64ae747
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changed control for aluop and naming
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2020-12-02 21:55:17 +08:00 |
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Ibrahim
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2a6d87c7b8
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Minor sytax corrections
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2020-12-02 13:35:47 +00:00 |
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Ibrahim
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56dfe9e1e8
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Minor sytax corrections
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2020-12-02 13:35:00 +00:00 |
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Aadi Desai
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bd9ae64dc2
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Update hardvard.v to match ALU
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2020-12-02 13:27:37 +00:00 |
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Ibrahim
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c4cae70ffc
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Added ALUZero Output + corrected other syntax errors
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2020-12-02 13:12:48 +00:00 |
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Ibrahim
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89abb5c1ed
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-02 12:52:37 +00:00 |
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Ibrahim
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57d15539a2
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Done expect for j type, LWL/R & MLT
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2020-12-02 12:51:53 +00:00 |
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yhp19
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63b017d552
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added control comments
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2020-12-02 15:43:30 +08:00 |
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Aadi Desai
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27cccc28b8
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Added partial loads to regfile
Partial reads are handled within the ALU
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2020-12-02 01:04:57 +00:00 |
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Aadi Desai
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3433337eba
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Added Regfile
Missing partial/misaligned loads
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2020-12-01 23:04:43 +00:00 |
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