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Added partial loads to regfile

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Partial reads are handled within the ALU
This commit is contained in:
Aadi Desai 2020-12-02 01:04:57 +00:00
parent 3433337eba
commit 27cccc28b8
2 changed files with 40 additions and 8 deletions
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15
rtl/mips_cpu_harvard.v
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@ -76,13 +76,14 @@ control control( //control flags block
regfile regfile(
.clk(clk), //clock input for triggering write port
.readreg1(rs),
.readreg2(rt),
.writereg(rd),
.writedata(writeback),
.regwrite(RegWrite),
.readdata1(read_data1),
.readdata2(read_data2),
.readreg1(rs), //read port 1 selector
.readreg2(rt), //read port 2 selector
.writereg(rd), //write port selector
.writedata(writeback), //write port input data
.regwrite(RegWrite), //enable line for write port
.opcode(opcode), //opcode input for controlling partial load weirdness
.readdata1(read_data1), //read port 1 output
.readdata2(read_data2), //read port 2 output
.regv0(register_v0) //debug output of $v0 or $2 (first register for returning function results
);

33
rtl/mips_cpu_regfile.v
View file

@ -5,6 +5,7 @@ input logic[4:0] readreg2, //read port 2 selector
input logic[4:0] writereg, //write port selector
input logic[31:0] writedata, //write port input data
input logic regwrite, //enable line for write port
input[5:0] opcode, //opcode input for controlling partial load weirdness
output logic[31:0] readdata1, //read port 1 output
output logic[31:0] readdata2, //read port 2 output
output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
@ -28,7 +29,37 @@ end
always_ff @(posedge clk) begin
if (regwrite) begin
memory[writereg] <= writedata;
case (opcode)
6'b100000: begin //lb, load byte
memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
end
6'b100100: begin //lbu, load byte unsigned
memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
end
6'b100001: begin //lh, load half-word
memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
end
6'b100101: begin //lhu, load half-word unsigned
memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
end
6'b100010: begin //lwl, load word left
case (readdata1[1:0])
2'b00: memory[writereg][31:24] <= writedata[7:0];
2'b01: memory[writereg][31:16] <= writedata[15:0];
2'b10: memory[writereg][31:8] <= writedata[23:0];
2'b11: memory[writereg][31:0] <= writedata[31:0];
endcase // readdata1[1:0]
end
6'b100110: begin //lwr, load word right
case (readdata1[1:0])
2'b00: memory[writereg][31:0] <= writedata[31:0];
2'b01: memory[writereg][23:0] <= writedata[31:8];
2'b10: memory[writereg][15:0] <= writedata[31:16];
2'b11: memory[writereg][7:0] <= writedata[31:24];
endcase // readdata1[1:0]
end
default: memory[writereg] <= writedata; //most instructions
endcase // opcode
end
end