Fix overall w.r.t iverilog compiler error

inputs/addu.txt

@@ -1,4 +1,4 @@
-350C0003
-350D0005
-018D5021
-01000008
+34040003
+34050005
+00851021
+00000008

inputs/reference.txt

@@ -20,10 +20,10 @@ ORI $5,$0,5
 ADDU $2,$4,$5
 JR $0
 
-350C0003
-350D0005
-018D5021
-01000008
+34040003
+34050005
+00851021
+00000008
 
 register_vo = 8
 

rtl/mips_cpu_alu.v

@@ -1,11 +1,11 @@
 module mips_cpu_alu(
-    input signed logic[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs. 
-    input signed logic[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
-    input logic [4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
-    input logic [4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from 
+    input logic signed[31:0] A, //Bus A - Input from the Readdata1 output from the reg file which corresponds to rs. 
+    input logic signed[31:0] B, //Bus B - Input from the Readdata2 output from the reg file which corresponds to rt.
+    input logic[4:0] ALUOp, // 5-bit output from Control that tells the alu what operation to do from a list of 20 distinct alu operations(see below).
+    input logic[4:0] shamt, //5-bit input used to specify shift amount for shift operations. Taken directly from the R-type instruction (Non-Variable) or from 
 
     output logic ALUCond, //If a relevant condition is met, this output goes high(Active High). Note: Relevant as in related to current condition being tested.
-    output signed logic[31:0] ALURes, // The ouput of the ALU 
+    output logic signed[31:0] ALURes // The ouput of the ALU 
 );
 
 /*  
@@ -64,7 +64,7 @@ Alu Operations:
 
 Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation quirks.
 
-assign ALUOps = ALUOp
+assign ALUOps = ALUOp;
 
   always_comb begin
 
@@ -88,43 +88,43 @@ assign ALUOps = ALUOp
       end
 
       AND: begin
-          ALUOut = A & B;
+          ALURes = A & B;
       end
 
       OR: begin
-          ALUOut = A | B;
+          ALURes = A | B;
       end
 
       XOR: begin
-          ALUOut = A^B;
+          ALURes = A^B;
       end
 
       SLL: begin
-          ALUOut = B << shamt;
+          ALURes = B << shamt;
       end
 
       SLLV: begin
-          ALUOut = B << A;
+          ALURes = B << A;
       end
 
       SRL: begin
-          ALUOut = B >> shamt;
+          ALURes = B >> shamt;
       end
 
       SRLV: begin
-          ALUOut = B >> A;
+          ALURes = B >> A;
       end
 
       SRA: begin
-          ALUOut = B >>> shamt;
+          ALURes = B >>> shamt;
       end
 
       SRAV: begin
-          ALUOut = B >>> A;
+          ALURes = B >>> A;
       end
    
       EQ: begin
-          if A == B begin
+          if (A == B) begin
             ALUCond = 1;
           end
           else begin
@@ -134,7 +134,7 @@ assign ALUOps = ALUOp
       end
 
       LES: begin
-          if A < B begin
+          if (A < B) begin
             ALUCond = 1;
           end
           else begin
@@ -144,17 +144,7 @@ assign ALUOps = ALUOp
       end
 
       LEQ: begin
-          if A <= B begin
-            ALUCond = 1;
-          end
-          else begin
-            ALUCond = 0;
-          end
-          
-      end
-
-      LEQ: begin
-          if A <= B begin
+          if (A <= B) begin
             ALUCond = 1;
           end
           else begin
@@ -164,7 +154,7 @@ assign ALUOps = ALUOp
       end
 
       GRT: begin
-          if A > B begin
+          if (A > B) begin
             ALUCond = 1;
           end
           else begin
@@ -174,7 +164,7 @@ assign ALUOps = ALUOp
       end
 
       GEQ: begin
-          if A >= B begin
+          if (A >= B) begin
             ALUCond = 1;
           end
           else begin
@@ -184,7 +174,7 @@ assign ALUOps = ALUOp
       end
 
       NEQ: begin
-          if A != B begin
+          if (A != B) begin
             ALUCond = 1;
           end
           else begin

rtl/mips_cpu_control.v

@@ -45,7 +45,7 @@ Memtoreg:
 
 //Commented signals represents dont care(x)
 
-module mips_cpu_control{
+module mips_cpu_control(
     input logic[5:0] Instr,
     input logic[5:0] rt,
     output logic[1:0] Regdst,
@@ -55,7 +55,7 @@ module mips_cpu_control{
     output logic Memwrite,
     output logic Alusrc,
     output logic Regwrite,
-    output logic Jump,
+    output logic Jump
     );
 
     always_comb begin
@@ -119,7 +119,7 @@ module mips_cpu_control{
                 //Memtoreg=;
                 Memwrite=0;
                 Alusrc=0;
-                Regwrite=0
+                Regwrite=0;
                 Jump=0;
             end
             6'd6: begin
@@ -206,7 +206,7 @@ module mips_cpu_control{
                 Regdst=2'b00;
                 Branch=0;
                 Memread=0;
-                Memtoreg=2b'00;
+                Memtoreg=2'b00;
                 Memwrite=0;
                 Alusrc=1;
                 Regwrite=1;

rtl/mips_cpu_harvard.v

@@ -23,13 +23,15 @@ module mips_cpu_harvard(
 //Control Flags
 logic Jump, Branch, ALUSrc, ALUZero, RegWrite;
 logic[5:0] ALUOp = instr_readdata[31:26];
-logic[999999999999999999999999999999999999999999999999999999999999999999:0] ALUFlags;
+logic[30:0] ALUFlags; //Not sure if this is needed anymore
 logic[1:0] RegDst, MemtoReg;
 
 //PC wires
 logic[31:0] pc_curr;
-logic[31:0] pc_next = Jump ? Jump_addr : PCSrc ? {pc_curr+4+{{14{instr_readdata[15]}}, instr_readdata[15:0], 2'b00}} : {pc_curr+4};
-logic[31:0] Jump_addr = {{pc_curr+4}[31:28], instr_readdata[25:0], 2'b00};
+logic[31:0] pc_curr_next = pc_curr + 3'd4; //Added due to compilation error
+logic[31:0] pc_delay; //Added due to compilation error
+logic[31:0] Jump_addr = {pc_curr_next[31:28], instr_readdata[25:0], 2'b00};
+logic[31:0] pc_next = Jump ? Jump_addr : PCSrc ? {pc_curr_next + {{14{instr_readdata[15]}}, instr_readdata[15:0], 2'b00}} : pc_curr_next;
 logic PCSrc = Branch && ALUZero;
 
 //Instruction MEM
@@ -54,7 +56,7 @@ assign data_address = ALUOut; //address to be written to comes from ALU
 assign data_writedata = read_data2; //data to be written comes from reg read bus 2
 
 //Writeback logic
-logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
+logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr_next} : MemtoReg==2'b01 ? data_readdata : ALUOut;
 
 always_ff @(posedge clk) begin
     pc_delay <= pc_curr;
@@ -67,16 +69,16 @@ pc pc(
 .pc_out(pc_curr)
 );
 
-control control( //control flags block
-.opcode(opcode), //opcode to be decoded
-.jump(Jump), //jump flag: 0 - increment or branch, 1 - J-type jump
-.branch(Branch), //branch flag: 0 - increment, 1 - branch if ALU.Zero == 1
-.memread(data_read), //tells data memory to read out data at dMEM[ALUout]
-.memtoreg(MemtoReg), //0: writeback = ALUout, 1: writeback = data_readdata
-.memwrite(data_write), //tells data memory to store data_writedata at data_writeaddress
-.alusrc(ALUSrc), //0: ALUin2 = read_data2, 1: ALUin2 = signextended(instr_readdata[15:0])
-.regwrite(RegWrite), //tells register file to write writeback to rd
-.regdst(RegDst) //select Rt, Rd or $ra to store to
+mips_cpu_control control( //control flags block
+.Instr(opcode), //opcode to be decoded
+.Jump(Jump), //jump flag: 0 - increment or branch, 1 - J-type jump
+.Branch(Branch), //branch flag: 0 - increment, 1 - branch if ALU.Zero == 1
+.Memread(data_read), //tells data memory to read out data at dMEM[ALUout]
+.Memtoreg(MemtoReg), //0: writeback = ALUout, 1: writeback = data_readdata
+.Memwrite(data_write), //tells data memory to store data_writedata at data_writeaddress
+.Alusrc(ALUSrc), //0: ALUin2 = read_data2, 1: ALUin2 = signextended(instr_readdata[15:0])
+.Regwrite(RegWrite), //tells register file to write writeback to rd
+.Regdst(RegDst) //select Rt, Rd or $ra to store to
 );
 
 regfile regfile(
@@ -91,19 +93,20 @@ regfile regfile(
 .readdata2(read_data2), //read port 2 output
 .regv0(register_v0) //debug output of $v0 or $2 (first register for returning function results
 );
-
+/*
 alucontrol alucontrol(
 .ALUOp(ALUOp), //opcode of instruction
 .funct(immediate[5:0]), //funct of instruction
 .aluflags(ALUFlags) //ALU Control flags
 );
-
-alu alu(
-.ALUFlags(ALUFlags), //selects the operation carried out by the ALU
+*/
+mips_cpu_alu alu(
+//.ALUFlags(ALUFlags), //selects the operation carried out by the ALU
 .A(alu_in1), //operand 1
 .B(alu_in2), //operand 2
-.ALUzero(ALUZero), //is the result zero, used for checks
-.ALUOut(ALUOut), //output/result of operation
-.shamt(shamt)
+.ALUCond(ALUZero), //is the result zero, used for checks
+.ALURes(ALUOut), //output/result of operation
+.shamt(shamt),
+.ALUOp(ALUOp)
 );
 endmodule : mips_cpu_harvard

rtl/mips_cpu_memory.v

@@ -42,18 +42,20 @@ module mips_cpu_memory(
         //Load contents from file if specified
         if (RAM_INIT_FILE != "") begin
             $display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
-            $readmemh(RAM_INIT_FILE, memory[3217031168:0]);
+            $readmemh(RAM_INIT_FILE, memory, 32'hBFC00000, 32'd0);
         end
     end
 
     //Combinatorial read path for data and instruction.
-    if (clk == 1) begin
-        assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
-        assign instr_readdata = memory[instr_address];
-    end
-    else begin
-        assign data_readdata = data_readdata;
-        assign instr_readdata = instr_address;
+    always_comb begin
+        if (clk == 1'd1) begin
+            data_readdata = data_read ? memory[data_address] : 16'hxxxx;
+            instr_readdata = memory[instr_address];
+        end
+        else begin
+            data_readdata = data_readdata;
+            instr_readdata = instr_address;
+        end
     end
 
 

rtl/mips_cpu_regfile.v

@@ -15,7 +15,7 @@ reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
 
 initial begin
 	integer i; //Initialise to zero by default
-    for (i = 0; i < 31; i++) begin
+    for (i = 0; i < 32; i++) begin
         memory[i] = 0;
     end
 end

test/test_mips_cpu_harvard.sh

@@ -29,7 +29,7 @@ then
     do
         # Run Each Testcase File
         echo ${TESTCASE}
-#        iverilog -g 2012 \
+#iverilog -g 2012 \
 #        -s mips_cpu_harvard_tb \
 #        -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/"${TESTCASE}\" \
 #        -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
@@ -37,13 +37,21 @@ then
     done
 
 else
-    echo "ELSE";
+    echo ${INSTR};
     # Run Testcase File Of Specified Instruction
-#    iverilog -g 2012 \
-#        -s mips_cpu_harvard_tb \
-#        -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.hex.txt\" \
-#        -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
-#           ${SRC}
+# Windows Iverilog with WSL
+#/mnt/c/Windows/System32/cmd.exe /C iverilog -g2012 \
+#    -s mips_cpu_harvard_tb \
+#    -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
+#    -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
+#    ${SRC}
+
+# Linux Iverilog
+iverilog -g2012 \
+    -s mips_cpu_harvard_tb \
+    -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
+    -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
+    ${SRC}
 fi
 
 #/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows

testbench/mips_cpu_harvard_tb.v

@@ -10,8 +10,30 @@ module mips_cpu_harvard_tb;
     logic data_read, data_write;
     logic[31:0] data_readdata, data_writedata, data_address;
 
-    mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);    
-    mips_cpu_harvard cpuInst(clk, reset, active, register_v0, clk_enable, instr_address, instr_readdata, data_address, data_write, data_read, data_writedata, data_readdata);
+    mips_cpu_memory #(RAM_INIT_FILE) ramInst(
+        .clk(clk), 
+        .data_address(data_address), 
+        .data_write(data_write), 
+        .data_read(data_read), 
+        .data_writedata(data_writedata), 
+        .data_readdata(data_readdata), 
+        .instr_address(instr_address), 
+        .instr_readdata(instr_readdata)
+    );    
+    mips_cpu_harvard cpuInst(
+        .clk(clk), 
+        .reset(reset), 
+        .active(active), 
+        .register_v0(register_v0), 
+        .clk_enable(clk_enable), 
+        .instr_address(instr_address), 
+        .instr_readdata(instr_readdata), 
+        .data_address(data_address), 
+        .data_write(data_write), 
+        .data_read(data_read), 
+        .data_writedata(data_writedata), 
+        .data_readdata(data_readdata)
+    );
 
     // Generate clock
     initial begin
@@ -37,14 +59,15 @@ module mips_cpu_harvard_tb;
         reset <= 0;
 
         @(posedge clk);
-        assert(running==1)
-        else $display("TB : CPU did not set running=1 after reset.");
+        assert(active==1) // Is this assert still valid?
+        else $display("TB : CPU did not set active=1 after reset.");
 
-        while (running) begin
+        while (active) begin
             @(posedge clk);
         end
 
         $display("TB : finished; running=0");
+        $display("%d",register_v0);
         $finish;
 
     end