20 commits

Author	SHA1	Message	Date
Aadi Desai	6c0554538c	Rename .v to .sv for Quartus to detect as SystemVerilog	2020-12-19 08:43:20 -08:00
jl7719	4f97fb41d8	Rename mips_cpu_memory.v to mips_cpu_harvard_memory.v	2020-12-18 09:55:41 +00:00
Aadi Desai	5c29ec2be1	Shorten testbench limit, remove custom bus script	2020-12-17 09:44:31 -08:00
Aadi Desai	cb29efd034	Merge branch 'main' into bus_wrapper	2020-12-17 16:46:01 +00:00
Aadi Desai	74681e8890	Stall bus memory when reset is high	2020-12-17 07:34:32 -08:00
jl7719	cfebb403ba	Delete from source files and the testbench	2020-12-17 15:02:59 +00:00
jl7719	2d9cca262d	Fix display appearing at the end of log file	2020-12-17 14:51:08 +00:00
Aadi Desai	2eccc5148e	Move bus memory from rtl to testbench folder	2020-12-17 13:58:07 +00:00
Aadi Desai	af29f22651	Merge branch 'main' into bus_wrapper ... Changes to be duplicated for bus version	2020-12-17 13:54:26 +00:00
jl7719	6e626c5931	Change location of the memory module from rtl to testbench	2020-12-17 10:32:52 +00:00
Aadi Desai	744aee097f	Modify bus tb to compile bus version instead	2020-12-16 20:15:08 +00:00
Aadi Desai	2f9b08a363	Updated bus tb to match harvard tb	2020-12-16 20:05:00 +00:00
jl7719	ec275418b7	Update harvard testbench regarding resets	2020-12-16 16:59:28 +00:00
jl7719	7150487472	Rename initialisation files	2020-12-13 14:54:53 +09:00
jl7719	943745a1e0	Tested all that can be tested for now ... Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus	2020-12-13 14:40:16 +09:00
jl7719	3594365a25	Create branch jl7719 ... Can test for normal pc incrementing instr	2020-12-11 19:45:13 +09:00
jl7719	c5aed43ab4	Update to test each instruction with a small memory	2020-12-09 16:47:58 +09:00
Ibrahim	11cabd3aea	changing module name	2020-12-07 10:52:01 +00:00
jl7719	c5167645e7	Fix overall w.r.t iverilog compiler error	2020-12-06 15:44:58 +09:00
jl7719	411f89110f	Add testbench related files	2020-12-04 23:44:48 +09:00