ELEC50010-IAC-CW/testbench
2020-12-19 08:43:20 -08:00
..
mips_cpu_bus_memory.sv Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00
mips_cpu_bus_tb.sv Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00
mips_cpu_harvard_memory.sv Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00
mips_cpu_harvard_tb.sv Rename .v to .sv for Quartus to detect as SystemVerilog 2020-12-19 08:43:20 -08:00