18 commits

Author	SHA1	Message	Date
Kacper	719c9ede2b	Added decoder logic for STR and LDR	2020-06-10 14:40:58 +01:00
Aadi Desai	a1cf89e644	Added LDR and STR to alu and set up data paths ... Decoder changes remaining	2020-06-10 14:02:15 +01:00
Aadi Desai	d046242bc1	Final State before Pipelining ... Debug Complete, data and instruction mifs + ram files. Test program checked	2020-06-09 22:45:20 +01:00
Kacper	2f6cbeae56	Debugging complete! ... The CPU works now except for the multiply commands. Pipelining is next! Woooo!	2020-06-08 23:07:52 +01:00
Kacper	24b293e24b	Recompiled certain files	2020-06-08 12:10:14 +01:00
Kacper	3d9ea175cd	Working on debugging ... The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.	2020-06-07 23:23:13 +01:00
Kacper	b527d5e77d	Debugging CPU	2020-06-07 20:51:33 +01:00
Kacper	9a1a1da664	Complete CPU v2 (not tested)	2020-06-07 16:12:05 +01:00
Kacper	685f69a7cf	Almost ready CPU ... Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.	2020-06-07 15:08:34 +01:00
Kacper	4318a5b70b	CPU completed	2020-06-04 16:33:27 +01:00
Kacper	1c0032fa95	Fixed decoder and SM	2020-06-02 20:09:22 +01:00
Kacper	cf179ad2cf	Revisions for testing	2020-05-27 18:53:59 +01:00
Kacper	e1acb56b66	Finished decoder	2020-05-27 18:53:03 +01:00
Kacper	5ed70dabb0	Working on datapath	2020-05-27 11:10:13 +01:00
Kacper	3b298e02a2	Finished datapath	2020-05-25 18:00:34 +01:00
Kacper	6b2363d6a1	Working on initial design	2020-05-25 17:16:24 +01:00
Benjamin	14418c8725	VCS Test	2020-05-20 19:24:20 +01:00
Aadi Desai	26c28a829d	Basic Project Setup	2020-05-20 12:44:57 +01:00