Alden0012
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3c60629d48
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Add scripts/rtl for formal verification
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2022-12-16 20:19:07 +00:00 |
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Alden0012
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5c4334ab76
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Merge branch 'main' of github.com:supleed2/hsvcw into main
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2022-12-12 16:16:23 +00:00 |
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Alden0012
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aabd220e6a
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Increase covergroups and test inputs for VGA, Integrate gpio checker in tb
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2022-12-12 16:16:17 +00:00 |
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Aadi Desai
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9c9536016b
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Format top tb and add vga image buffer reset task
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2022-12-12 16:05:01 +00:00 |
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Alden0012
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f586cd95d9
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Add VGA and GPIO checker
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2022-12-05 16:55:23 +00:00 |
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Alden0012
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128a2a9eaa
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Fix GPIO assertions and test-bench coverage and constraints
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2022-11-14 15:28:45 +00:00 |
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Alden0012
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f2b3a72a54
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Add initial GPIO test-bench
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2022-11-14 10:24:11 +00:00 |
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Aadi Desai
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c83b8a73f1
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Switch all Verilog files to SystemVerilog file endings
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2022-11-07 12:58:43 +00:00 |
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Aadi Desai
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dcdda4d9e1
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Initial Commit
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2022-11-07 12:41:05 +00:00 |
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